Abstract: A substrate composed of hexagonally crystalline SiC is prepared such that its main surface is in the direction at which the minimum angle between the main surface and a plane perpendicular to the (0001) plane is one degree or less, for example, in the direction at which the minimum angle between the main surface and the [0001] direction, which is perpendicular to the (0001) plane, is one degree or less. A horizontal semiconductor device is formed on one main surface of the substrate prepared by the foregoing method. Thus, it was possible to improve the value of breakdown voltage significantly over the horizontal semiconductor device in which the main surface of the substrate composed of hexagonally crystalline SiC is in the direction along the (0001) direction.

Abstract: Method for forming a structure provided with at least one zone of one or several semiconductor nanocrystals (13). It consists in: exposing with a beam of electrons (11) at least one zone (12) of a semiconductor film (1) lying on an electrically insulating support (2), the exposed zone (12) contributing to defining at least one dewetting zone (10) of the film (1), annealing the film (1) at high temperature in such a way that the dewetting zone (10) retracts giving the zone of one or several nanocrystals (13).

Abstract: High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include a cap layer having a doped region adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. Graphitic BN passivation structures for wide bandgap semiconductor devices are provided. SiC passivation structures for Group III-nitride semiconductor devices are provided. Oxygen anneals of passivation structures are also provided. Ohmic contacts without a recess are also provided.

Abstract: An organic electroluminescent display device includes first and second substrates facing and spaced apart from each other. A first electrode resides on the first substrate and a separator having dual-layer, reciprocal L-shaped pattern resides on the first electrode. An organic emitting layer having a first thickness resides on the first electrode in a sub-pixel region and a second electrode resides on the organic emitting layer. An array element layer resides on the second substrate, the array element layer including a thin film transistor. A connection pattern electrically connects the second electrode and the thin film transistor.

Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.

Abstract: According to an exemplary embodiment, a PHEMT (pseudomorphic high electron mobility transistor) structure includes a conductive channel layer. The PHEMT structure further includes at least one doped layer situated over the conductive channel layer. The at least one doped layer can include a heavily doped layer situated over a lightly doped layer. The PHEMT structure further includes a recessed ohmic contact situated on the conductive channel layer, where the recessed ohmic contact is situated in a source/drain region of the PHEMT structure, and where the recessed ohmic contact extends below the at least one doped layer. According to this exemplary embodiment, the recessed ohmic contact is bonded to the conductive channel layer. The recessed ohmic contact is situated adjacent to the at least one doped layer. The PHEMT structure further includes a spacer layer situated between the at least one doped layer and the conductive channel layer.

Abstract: Provided is a method of fabricating a Schottky barrier transistor. The method includes (a) forming a pair of cavities for forming a source forming portion and a drain forming portion having a predetermined depth and parallel to each other and a channel forming portion having a fin shape between the cavities in a substrate; (b) filling the pair of cavities with a metal; (c) forming a channel, a source, and a drain by patterning the channel forming portion, the source forming portion, and the drain forming portion in a direction perpendicular to a lengthwise direction of the channel forming portion; (d) sequentially forming a gate oxide layer and a gate metal layer that cover the channel, the source, and the drain on the substrate; and (e) forming a gate electrode corresponding to the channel by patterning the gate metal layer, wherein one of the operations (b) through (e) further comprises forming a Schottky barrier by annealing the substrate.

Abstract: A method of making a semiconductor device includes forming a p-type semiconductor region to an n-type semiconductor substrate in such a manner that the p-type semiconductor region is partially exposed to a top surface of the semiconductor substrate, forming a Schottky electrode of a first material in such a manner that the Schottky electrode is in Schottky contact with an n-type semiconductor region exposed to the top surface of the semiconductor substrate, and forming an ohmic electrode of a second material different from the first material in such a manner that the ohmic electrode is in ohmic contact with the exposed p-type semiconductor region. The Schottky electrode is formed earlier than the ohmic electrode.

Abstract: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.

Abstract: A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. Source and drain contacts of the D-mode and E-mode FETs are coupled to the ohmic contact layer. A gate contact of the D-mode and E-mode FETs is coupled to the barrier layer. An amorphized region is provided beneath the E-mode gate contact within the barrier layer. The amorphized region forms a buried E-mode Schottky contact with the barrier layer. An alternative embodiment couples the gate contact of the D-mode transistor to a first layer that overlies the barrier layer, and provides a similar D-mode amorphized region within the first layer.

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Abstract: A main semiconductor region of semiconducting nitrides is formed on a silicon substrate via a buffer region of semiconducting nitrides to provide devices such as HEMTs, MESFETs and LEDs. In order to render the wafer proof against warping, the buffer region is divided into a first and a second multilayered buffer subregion. The first buffer subregion comprises multiple alterations of a multi-sublayered first buffer layer and a non-sublayered second buffer layer. Each multi-sublayered first buffer layer of the first buffer subregion comprises multiple alternations of a first and a second buffer sublayer. The second buffer sublayers of each multi-sublayered first buffer layer either do not contain aluminum or do contain it in a higher proportion than do the first buffer sublayers. The second multilayered buffer subregion comprises multiple alternations of a first and a second buffer layer.

Abstract: A method for fabricating a semiconductor device includes: forming a dummy gate that defines a region in which a gate electrode should be formed on a semiconductor substrate; forming a surface film on the semiconductor substrate by directional sputtering vertical to a surface of the semiconductor substrate, the directional sputtering being one of collimate sputtering, long throw sputtering and ion beam sputtering; removing the surface film formed along a sidewall of the dummy gate; removing the dummy gate; and forming the gate electrode in the region from which the dummy gate on the semiconductor substrate has been removed.

Abstract: Dual channel heterostructures comprising strained Si and strained Ge-containing layers are disclosed, along with methods for producing such structures. In preferred embodiments, a strain-relaxed buffer layer is deposited on a carrier substrate, a strained Si layer is deposited over the strain-relaxed buffer layer and a strained Ge-containing layer is deposited over the strained Si layer. The structure can be transferred to a host substrate to produce the strained Si layer over the strained Ge-containing layer. By depositing the Si layer first, the process avoids Ge agglomeration problems.

Abstract: A J-FET includes a channel layer of a first conductivity type (a Si-doped n-type AlGaAs electron supply layers 3 and 7, undoped AlGaAs spacer layers 4 and 6, and an undoped InGaAs 5 channel layer 5) formed above a semi-insulating GaAs substrate, an upper semiconductor layer made up of at least one semiconductor layer and formed above the channel layer of the first conductivity type, a semiconductor layer of a second conductivity type (C-doped p+-GaAs layer 18) formed in a recess made in the upper semiconductor layer or formed above the upper semiconductor layer, a gate electrode placed above and in contact with the semiconductor layer of the second conductivity type, and a gate insulating film including a nitride film formed above and in contact with the upper semiconductor layer and an oxide film formed above the nitride film and having a larger thickness than the nitride film.

Abstract: An integrated circuit structure is described, and includes a substrate, a contact window, and a Schottky contact metal layer. A heavily doped region and a lightly doped region are formed in the substrate. The contact window is disposed above the heavily doped region, and the Schottky contact metal layer is disposed above the lightly doped region. The Schottky contact metal layer and the substrate form a Schottky diode. The material of the contact window is different from that of the Schottky contact metal layer.

Abstract: A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. Semiconductor device layers are deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.

Abstract: Group III-Nitride semiconductor device structures and methods of fabricating Group III-Nitride structures are provided that include an electrically conductive Group III-Nitride substrate, such as a GaN substrate, and a semi-insulating or insulating Group III-Nitride epitaxial layer, such as a GaN epitaxial layer, on the electrically conductive Group III-Nitride substrate. The Group III-Nitride epitaxial layer has a lattice constant that is and a composition that may be substantially the same as a composition and a lattice constant of the Group III-Nitride substrate.

Abstract: A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes.

Abstract: The production of a microelectronic component, particularly a pHEMT, having a T-shaped gate electrode in a double-recess structure uses a production method for self-adjusting alignment of the two recesses of the double-recess structure and of the gate foot of the gate electrode.

Abstract: A thin film transistor array (TFT) substrate and a method for manufacturing the same are provided. The manufacturing method needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs not to form a contact window in a relative thick film layer such as a planarization layer or a color filter layer, so as to connect the pixel electrode to the source/drain, thus the difficulty of the manufacturing process is effectively reduced.

Abstract: Methods of manufacturing a semiconductor device and resulting products. The semiconductor device includes a semiconductor substrate, a hetero semiconductor region hetero-adjoined with the semiconductor substrate, a gate insulation layer contacting the semiconductor substrate and a heterojunction of the hetero semiconductor region, a gate electrode formed on the gate insulation layer, an electric field alleviation region spaced apart from a heterojunction driving end of the heterojunction that contacts the gate insulation layer by a predetermined distance and contacting the semiconductor substrate and the gate insulation layer, a source electrode contacting the hetero semiconductor region and a drain electrode contacting the semiconductor substrate. A mask layer is formed on the hetero semiconductor region, and the electric field alleviation region and the heterojunction driving end are formed by using at least a portion of the first mask layer.

Abstract: A nitride semiconductor device, which includes a III-V Group nitride semiconductor layer being composed of a III Group element consisting of at least one of a group containing of gallium, aluminum, boron and indium and V Group element consisting of at least nitrogen among a group consisting of nitrogen, phosphorus and arsenic, including a first nitride semiconductor layer including the III-V Group nitride semiconductor layer being deposited on a substrate, a second nitride semiconductor layer including the III-V Group nitride semiconductor layer being deposited on the first nitride semiconductor and not containing aluminum and a control electrode making Schottky contact with the second nitride semiconductor layer wherein the second nitride semiconductor layer includes a film whose film forming temperature is lower than the first nitride semiconductor layer.

Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode.

Abstract: A substrate arrangement for high power semiconductor devices includes a SiC wafer having a Si layer deposited on a surface of the SiC wafer. An SOI structure having a first layer of Si, an intermediate layer of SiO2 and a third layer of Si, has its third layer of Si bonded to the Si deposited on the SiC wafer, forming a unitary structure. The first layer of Si and the intermediate layer of SiO2 of the SOI are removed, leaving a pure third layer of Si on which various semiconductor devices may be fabricated. The third layer of Si and deposited Si layer may be removed over a portion of the substrate arrangement such that one or more semiconductor devices may be fabricated on the SiC wafer while other semiconductor devices may be accommodated on the pure third layer of Si.

Abstract: A method for fabricating devices in a multi-layer structure adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors includes defining gate recesses in the structure. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

Abstract: A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel.

Abstract: A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n+-doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.

Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a main surface of a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region in circular form, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.

Abstract: A semiconductor device is formed on a semiconductor substrate. The semiconductor device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and the body into the drain, an active region contact electrode disposed within the active region contact trench, wherein the active region contact electrode and the drain form a Schottky diode, and a Schottky barrier controlling layer disposed in the epitaxial layer adjacent to the active region contact trench.

Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer 24 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.

Abstract: One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a silicon germanium (Si—Ge) layer. In various embodiments, the well region includes a number of recombination centers between the Si—Ge layer and the insulation layer. A source region, a drain region, a gate oxide layer, and a gate are formed. In various embodiments, the Si—Ge layer includes a number of recombination centers in the source/drain regions. In various embodiments, a metal silicide layer and a lateral metal Schottky layer are formed above the well region to contact the source region and the well region. Other aspects are provided herein.

Abstract: A method of compensating resistivity of a near-surface region of a substrate includes epitaxially growing a buffer layer on the substrate, wherein the buffer is grown as having a dopant concentration as dependent on resistivity and conductivity of the substrate, so as to deplete residual or excess charge within the near-surface region of the substrate. The dopant profile of the buffer layer be smoothly graded, or may consist of sub-layers of different dopant concentration, to also provide a highly resistive upper portion of the buffer layer ideal for subsequent device growth. Also, the buffer layer may be doped with carbon, and aluminum may be used to getter the carbon during epitaxial growth.

Abstract: One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a second diffusion region formed in the body region. A channel region is formed in the body region between the first diffusion region and the second diffusion region. The memory cell includes a gate insulator stack formed above the channel region, and a gate to connect to a word line. The gate insulator stack includes a floating plate to selectively hold a charge. The floating plate is connected to the second diffusion region. The memory cell includes a diode that connects the body region to the second diffusion region such that the floating plate is charged when the diode is reversed biased. Other aspects are provided herein.

Abstract: The present invention relates to a high voltage and high power gallium nitride (GaN) transistor structure. In general, the GaN transistor structure includes a sub-buffer layer that serves to prevent injection of electrons into a substrate during high voltage operation, thereby improving performance of the GaN transistor structure during high voltage operation. Preferably, the sub-buffer layer is aluminum nitride, and the GaN transistor structure further includes a transitional layer, a GaN buffer layer, and an aluminum gallium nitride Schottky layer.

Abstract: A semiconductor component, particularly a pHEMT, having a T-shaped gate electrode deposited in a double-recess structure, is produced with a method with self-adjusting alignment of the recesses and of the T-shaped gate electrode.

Abstract: A semiconductor device (100) is formed on a semi-insulating semiconductor substrate (101) including a channel layer (104), a spacer layer (105), an electron supply layer (106), and a barrier layer (108). A composite layer (110) is formed over the barrier layer (108). A metal (116) is deposited over the composite layer (110). The metal (116) is annealed to promote a chemical reaction between the metal (116) and the composite layer (110) in which a portion of the metal sinks into the composite layer (110) and forms an ohmic contact with the composite layer.

Abstract: Transistor fabrication includes forming a nitride-based channel layer on a substrate, forming a barrier layer on the nitride-based channel layer, forming a contact recess in the barrier layer to expose a contact region of the nitride-based channel layer, forming a contact layer on the exposed contact region of the nitride-based channel layer, for example, using a low temperature deposition process, forming an ohmic contact on the contact layer and forming a gate contact disposed on the barrier layer adjacent the ohmic contact. A high electron mobility transistor (HEMT) and methods of fabricating a HEMT are also provided.

Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a plurality of gate structures on a substrate, each gate structure including a first electrode layer for a floating gate; forming a first insulation layer covering the gate structures and active regions located at each side of the gate structures; forming a second electrode layer over the first insulation layer; and forming a plurality of control gates on the active regions located at each side of the gate structures by performing an etch-back process to the second electrode layer.

Abstract: A method of forming a rectifying diode. The method comprises providing a first semiconductor region of a first conductivity type and having a first dopant concentration and forming a second semiconductor region in the first semiconductor region. The second semiconductor region has the first conductivity type and having a second dopant concentration greater than the first dopant concentration. The method also comprises forming a conductive contact to the first semiconductor region and forming a conductive contact to the second semiconductor region. The rectifying diode comprises a current path, and the path comprises: (i) the conductive contact to the first semiconductor region; (ii) the first semiconductor region; (iii) the second semiconductor region; and (iv) the conductive contact to the second semiconductor region. The second semiconductor region does not extend to a layer buried relative to the first semiconductor region.

Abstract: A compound semiconductor device has: a substrate; a GaN channel layer; an n-type AlqGal-qN (0<q (1) electron supply layer; an n-type GaN cap layer; a gate electrode disposed on the cap layer and forming a Schottky contact; recesses formed on both sides of the gate electrode on source and drain sides by at least partially removing the cap layer, the recesses having a bottom surface of a roughness larger than a roughness of a surface of the cap layer under the gate electrode; a source electrode disposed on the bottom surface of the recess on the source side; and a drain electrode disposed on the bottom surface of the recess on the drain side.

Abstract: Exemplary embodiments of the invention provide techniques that enable avoidance of the concentration of an electric field at the edge of a semiconductor film in a semiconductor device such as a thin film transistor, thereby enhancing the reliability. Exemplary embodiments provide a method of manufacturing a semiconductor device using a structure in which a semiconductor film, a dielectric film, and an electrode are deposited.

Abstract: A method and resulting high electron mobility transistor comprised of a substrate and a relaxed silicon-germanium layer formed over the substrate. A dopant layer is formed within the relaxed silicon-germanium layer. The dopant layer contains carbon and/or boron and has a full-width half-maximum (FWHM) thickness value of less than approximately 70 nanometers. A strained silicon layer is formed over the relaxed silicon-germanium layer and is configured to act as quantum well device.

Abstract: A semiconductor structure a structure with an enhancement mode transistor device disposed in a first region and depletion mode transistor device disposed in a laterally displaced second region. The structure has a channel layer for the depletion mode and enhancement mode transistor devices. An enhancement mode transistor device InGaP etch stop/Schottky contact layer is disposed over the channel layer; a first layer different from InGaP disposed on the InGaP layer; a depletion mode transistor device etch stop layer is disposed on the first layer; and a second layer disposed on the depletion mode transistor device etch stop layer. The depletion mode transistor device has a gate recess passing through the second layer and the depletion mode transistor device etch stop layer and terminating in the first layer. The enhancement mode transistor device has a gate recess passing through the second layer, the depletion mode transistor device etch stop layer, the first layer, and terminating in the InGaP layer.

Abstract: Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different type FETs is different and is pre-selected to optimize performance. For example, a p-FET gate electrode material can have a work function near the valence band and an n-FET gate electrode material can have a work function near the conduction band. The first gate electrodes of the first FET are located adjacent to the sidewall channels and the second gate electrode of the second FET is located above the planar channel. However, the device structure is unique in that the second gate electrode extends laterally above the first FET and is electrically coupled to the first gate electrodes.

Abstract: A nitride semiconductor device enabiling to supress current collapse and manufacturing method thereof including a III-V group nitride semiconductor layer formed of III group elements includes at least one element from the group consisting of gallium, aluminum, boron and indium, and V group elements including at least nitrogen from the group consisting of nitrogen, phosphorous and arsenic, comprising a first nitride semiconductor layer made of said III-V group nitride semiconductor layer deposited on a substrate, a second nitride semiconductor layer comprising said III-V group nitride semiconductor layer and a control electrode making Schottky contact with the first nitride semiconductor layer being exposed through removing a portion of the second semiconductor layer.

Abstract: After a bottom electrode film is formed, a ferroelectric film is formed on the bottom electrode film. Then, a heat treatment is performed for the ferroelectric film in an oxidizing atmosphere so as to crystallize the ferroelectric film. Then, a top electrode film is formed on the ferroelectric film. In the heat treatment (i.e., annealing for crystallization), a flow rate of oxidizing gas is set to be in a range of from 10 sccm to 100 sccm.

Abstract: This invention pertains to an electronic device and to a method for making it. The device is a heterojunction transistor, particularly a high electron mobility transistor, characterized by presence of a 2 DEG channel. Transistors of this invention contain an AlGaN barrier and a GaN buffer, with the channel disposed, when present, at the interface of the barrier and the buffer. Surface treated with ammonia plasma resembles untreated surface. The method pertains to treatment of the device with ammonia plasma prior to passivation to extend reliability of the device beyond a period of time on the order of 300 hours of operation, the device typically being a 2 DEG AlGaN/GaN high electron mobility transistor with essentially no gate lag and with essentially no rf power output degradation.

Abstract: The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the source and has an end that extends towards the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel region and is electrically coupled to the source. An n-type conductivity region is provided on the p-type conductivity region beneath the source region and extending toward the drain region without extending beyond the end of the p-type conductivity region. Related methods of fabricating MESFETS are also provided.

Abstract: A semiconductor device has a Group III nitride semiconductor layer and a gate electrode formed on the Group III nitride semiconductor layer. The gate electrode contains an adhesion enhancing element. A thermally oxidized insulating film is interposed between the Group III nitride semiconductor layer and the gate electrode.