Abstract: A system and method for isolating semiconductor devices is provided. An embodiment comprises an isolation region that is laterally removed from source/drain regions of semiconductor devices and has a dielectric material extending over the isolation implant between the source/drain regions. The isolation region may be formed by forming an opening through a layer over the substrate, depositing a dielectric material along the sidewalls of the opening, implanting ions into the substrate after the deposition, and filling the opening with another dielectric material.

Abstract: The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit.

Abstract: A photo detector and related fabricating method are disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer. The patterned conductive layer is disposed on the dielectric layer. The inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region.

Abstract: There is provided an apparatus including an image sensor of a back-illuminated type using a complementary metal oxide semiconductor (CMOS), including a light receiving unit, formed in a semiconductor substrate, which receives incident light, an anti-reflection film formed on a back-surface side of the semiconductor substrate in which the light receiving unit is formed, and a silicon oxide film, formed on a back-surface side of the anti-reflection film, which has a refractive index lower than a silicon nitride film and has a higher density in a back-surface side than in a front-surface side thereof.

Abstract: A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector.

Abstract: An electrostatic discharge device and an organic electro-luminescence display device having the same are provided. The organic electro-luminescence display device includes an electrostatic discharge device including a metal pattern having an island shape on a substrate, an insulating layer on the metal pattern, a semiconductor pattern on the insulating layer, the semiconductor pattern corresponding to the metal pattern, a first electrode overlapping one end of the semiconductor pattern, and a second electrode overlapping the other end of the semiconductor pattern, and spaced from the first electrode, thereby preventing a current leakage, a signal distortion and a signal cross-talk to improve the reliability.

Abstract: A display device includes: a first substrate; a photo transistor on the first substrate; and a switching transistor connected to the photo transistor. The photo transistor includes a light blocking film on the first substrate, a first gate electrode on the light blocking film and in contact with the light blocking film, a first semiconductor layer on the first gate electrode and overlapping the light blocking film, and a first source electrode and a first drain electrode on the first semiconductor layer. The switching transistor includes a second gate electrode on the first substrate, a second semiconductor layer on the second gate electrode and overlapping the second gate electrode, and a second source electrode and a second drain electrode on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are at a same layer of the display device, and each includes crystalline silicon germanium.

Abstract: Embodiments of radiographic imaging systems; radiography detectors and methods for using the same; and/or fabrication methods therefore can include radiographic imaging array that can include a plurality of pixels that each include a photoelectric conversion element coupled to a thin-film switching element. In certain exemplary embodiments, thin-film switching element is a metal oxide (e.g., a-IGZO) TFT manufactured using a reduce photolithography mask counts. In certain exemplary embodiments, the thin-film switching element is a metal oxide (e.g., a-IGZO) TFT that includes reduced lower alignment tolerances between TFT electrodes. In certain exemplary embodiments, the thin-film switching element is a metal oxide (e.g., a-IGZO) TFT including a reduced thickness active layer.

Abstract: A method of making a semiconductor light-emitting device including (A) a light-emitting portion by laminating in sequence a first compound semiconductor layer, an active layer, and a second compound semiconductor layer; (B) a first electrode electrically connected to the first compound semiconductor layer; (C) a transparent conductive material layer on the second compound semiconductor layer; (D) an insulating layer on a transparent conductive material layer; and (E) a second reflective electrode that on the transparent conductive material layer and on the insulating layer in a continuous manner, wherein, that the areas of the active layer, the transparent conductive material layer, the insulating layer, and the second electrode S1, S2, S3, and S4, respectively are related as S1?S2<S3 and S2<S4.

Abstract: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel region and a periphery region, forming a light sensing element on the pixel region, and forming at least one transistor in the pixel region and at least one transistor in the periphery region. The step of forming the at least one transistor in the pixel region and periphery region includes forming a gate electrode in the pixel region and periphery region, depositing a dielectric layer over the pixel region and periphery region, partially etching the dielectric layer to form sidewall spacers on the gate electrode and leaving a portion of the dielectric layer overlying the pixel region, and forming source/drain (S/D) regions by ion implantation.

Abstract: The method of the invention includes the sequential steps of providing a plurality of solar cells, interconnecting the solar cells using one or more interconnect tabs, attaching the interconnect tabs to a top side of the solar cell to interconnect the plurality of solar cells by coupling an exposed top surface of a first solar cell to a top surface of an adjacent second solar cell, attaching one or more bypass diodes to a top side of the solar cell, then next applying an adhesive to a first film layer, placing the plurality of solar cells onto the first film layer, then next applying an adhesive to a second film layer, placing the plurality of solar cells and first film layer onto the second film layer to form a sheet assembly, and then forming the solar sheet from the sheet assembly.

Abstract: Fabrication of a single crystal silicon solar cell with an insitu epitaxially deposited very highly doped p-type silicon back surface field obviates the need for the conventional aluminum screen printing step, thus enabling a thinner silicon solar cell because of no aluminum induced bow in the cell. Furthermore, fabrication of a single crystal silicon solar cell with insitu epitaxial p-n junction formation and very highly doped n-type silicon front surface field completely avoids the conventional dopant diffusion step and one screen printing step, thus enabling a cheaper manufacturing process.

Abstract: A method is provided to isolated conductive pads on top of a multi-layer polymer device structure. The method utilizes laser radiation to ablate conductive material and create a non-conductive path, electrically isolating the conductive pads. The process is self-limiting and incorporates at least one layer within the stack that absorbs the radiation at the required wavelength. The prevention of radiation degradation of the underlying layers is achieved, as absorption of radiation occurs primarily on the surface of the structure, but not in any of the radiation sensitive underlying layers of the electronic device. The method preferably uses low energy infrared radiation which has been shown to produce little debris and no device degradation.

Abstract: An optically controlled read only memory is disclosed. The optically controlled read only memory includes a substrate, a plurality of memory cells having optical sensors disposed on the substrate, and at least one shielding structure disposed on the optical sensor, in which the shielding structure selectively shields a portion of the optical sensor according to a predetermined layout. Preferably, the optically controlled read only memory of the present invention is capable of providing two types or more program codes and outputting different program codes carrying different function under different lighting condition.

Abstract: A method of manufacturing a backside illumination image sensor includes forming an epitaxial layer on a silicon (Si) substrate, and forming an inter-metal dielectric (IMD) on the epitaxial layer. The method includes forming a trench in one side region of the epitaxial layer, forming an insulating layer at a side wall and bottom of the trench, forming a color filter and microlens on the IMD, bonding a support wafer onto the IMD with the color filter and microlens formed therein, and/or removing the Si substrate.

Abstract: An active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is disposed on the display area of the substrate. A gate insulator is disposed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are disposed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then disposed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is disposed on the passivation layer.

Abstract: A photronic device includes a substrate having an opening through the substrate. The photronic device further includes an insulating layer over the substrate including over the opening. The photronic device further includes an active layer over the insulating layer. The photronic device further includes a photoactive device formed in the active layer, wherein the photoactive device is over the opening. The photronic device further includes active electronic circuitry formed in the active layer. The photronic device further includes a reflective layer on the insulating layer in the opening.

Abstract: A photoelectric conversion element including a first gate electrode, a first gate insulating layer, a crystalline semiconductor layer, an amorphous semiconductor layer, an impurity semiconductor layer, a source electrode and a drain electrode in contact with the impurity semiconductor layer, a second gate insulating layer covering a region between the source electrode and the drain electrode, and a second gate electrode over the second gate insulating layer. In the photoelectric conversion element, a light-receiving portion is provided in the region between the source electrode and the drain electrode, the first gate electrode includes a light-shielding material and overlaps with the entire surface of the crystalline semiconductor layer and the amorphous semiconductor layer, the second gate electrode includes a light-transmitting material and overlaps with the light-receiving portion, and the first gate electrode is electrically connected to the source electrode or the drain electrode is provided.

Abstract: A photoelectric conversion device has a high S/N ratio and can increase the detection efficiency even under a low luminance. The photoelectric conversion device generates an increased electric charge by impact ionization in a photoelectric conversion unit formed from a chalcopyrite type semiconductor, so as to improve dark current characteristic.

Abstract: Provided herein are methods of incorporating additives into thin-film solar cell substrates and back contacts. In certain embodiments, sodium is incorporated into a substrate or a back contact of a thin-film photovoltaic stack where it can diffuse into a CIGS or other absorber layer to improve efficiency and/or growth of the layer. The methods involve laser treating the substrate or back contact in the presence of a sodium (or sodium-containing) solid or vapor to thereby incorporate sodium into the surface of the substrate or back contact. In certain embodiments, the surface is simultaneously smoothed.

Abstract: Methods of fabricating bypass diodes for solar cells are described. In one embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed on the first conductive region. In another embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed within, and surrounded by, an uppermost portion of the first conductive region but is not formed in a lowermost portion of the first conductive region.

Abstract: A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion.

Abstract: Methods of manufacturing photovoltaic modules are provided. One method includes providing a substrate and depositing a lower electrode above the substrate. The method also includes depositing a lower stack of microcrystalline silicon layers above the lower electrode, depositing an upper stack of amorphous silicon layers above the lower stack of microcrystalline silicon layers, and depositing an upper electrode above the upper stack of amorphous silicon layers. At least one of the lower stack and the upper stack includes an N-I-P stack of silicon layers having an n-doped silicon layer, an intrinsic silicon layer, and a p-doped silicon layer. The intrinsic silicon layer has an energy band gap that is reduced by depositing the intrinsic silicon layer at a temperature of at least 250 degrees Celsius.

Abstract: The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.

Abstract: A method for producing a thin-film solar cell with a cell level integrated bypass diode includes forming at least first, second and third series-connected cells on a support, each cell being a laminated structure comprising a junction layer including semiconducting material of a first and second type, a front electrode formed of a transparent conductive oxide resistant to an etchant disposed in electrical contact with the semiconducting material of the first type, and a back electrode in electrical contact with the semiconducting material of the second type. A portion of both the back electrode and the junction layer are separated from a selected parent solar cell. Using the separated portion of the back electrode the semiconducting material of the second type of the separated portion of the junction layer is connected to the semiconducting material of the first type of any one chosen solar cell in the array.

Abstract: A method for manufacturing a backside-illuminated image sensor includes (1) forming an isolation film on the front side of a semiconductor substrate with a buried insulating layer formed therein to define an active region; (2) forming a light-receiving element in the active region of the semiconductor substrate; and (3) forming an inter-layer dielectric layer on the front side of the semiconductor substrate on which the light-receiving element is formed. The method may include forming a super contact hole to pass through the inter-layer dielectric layer and the buried insulating layer in a pad region defined on the front side of the semiconductor substrate reaching the semiconductor substrate. The method may include forming a barrier layer of a metal oxide film containing transition metal at the bottom and sidewall of the super contact hole. The method may include filling a conductive material in the super contact hole, in which the barrier layer is formed, to form a super contact.

Abstract: A method for forming copper indium gallium (sulfide) selenide (CIGS) solar cells, cadmium telluride (CdTe) solar cells, and copper zinc tin (sulfide) selenide (CZTS) solar cells using laser annealing techniques to anneal the absorber and/or the buffer layers. Laser annealing may result in better crystallinity, lower surface roughness, larger grain size, better compositional homogeneity, a decrease in recombination centers, and increased densification. Additionally, laser annealing may result in the formation of non-equilibrium phases with beneficial results.

Abstract: A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion.

Abstract: A light receiving element includes a waveguide that includes a waveguide core, a multi-mode interference waveguide that has a width larger than a width of the waveguide, the multi-mode interference waveguide receiving a first light from the waveguide core at a first end, and a photodetection portion that includes a first semiconductor layer and an absorption layer disposed on the first semiconductor layer, the first semiconductor layer including at least one layer and receiving a second light from the multi-mode interference waveguide at a second end, the absorption layer being disposed above the first semiconductor layer and absorbing the second light. A distance from the first end of the multi-mode interference waveguide to the second end of the photodetection portion is longer than 70% of a first length and shorter than 100% of the first length, the first length being a length where self-imaging occurs in the multi-mode interference waveguide.

Abstract: Disclosed is a method of fabricating a thin film solar cell. A separation process (‘P4’ process) of insulating a thin film solar cell from the outside is integrally performed with a transparent electrode patterning process (‘P1’ process) and a metallic electrode patterning process (‘P3’ process). This may reduce the fabrication costs and enhance spatial efficiency as the ‘P4’ process and equipment for the ‘P4’ process are not required.

Abstract: Provided herein are methods of polishing, cleaning and texturing back contacts of thin-film solar cells. According to various embodiments, the methods involve irradiating sites on the back contact with laser beams to remove contaminants and/or smooth the surface of the back contact. The back contact, e.g., a molybdenum, copper, or niobium thin-film, is smoothed prior to deposition of the absorber and other thin-films of the photovoltaic stack. In certain embodiments, laser polishing of the back contact is used to enhance the diffusion barrier characteristics of the back contact layer, with all or a surface layer of the back contact becoming essentially amorphous. In certain embodiments, the adhesion of the absorber layer is enhanced by the textured back contact and by the presence of the amorphous metal at the deposition surface.

Abstract: A structure of stacking chips and a method for manufacturing the structure of stacking chips are provided. A wafer with optical chips and a glass substrate with signal processing chips are stacked with each other, and then subjected to ball mounting and die sawing to form the stacked packaging structure. The optical chips and the signal processing chips form the electrical connection on the surface of the glass substrate via the through holes thereof.

Abstract: A solid-state image sensing device has a plurality of detection units periodically arranged as a two-dimensional array on a substrate. Each of the detection units includes a visible light detector and an infrared light detector arranged on the same optical axis in a vertical direction so that the visible light detector and the infrared light detector overlap with each other. Each of the detection units also includes a signal readout circuit provided in the substrate so as to output signals of the visible light detector and the infrared light detector as time-series signals.

Abstract: A display device and a method of manufacturing the same, the display includes: an electrode plate operable to have a radio-frequency wave to pass therethrough; a light-emitting portion disposed in a direction of one surface of the electrode plate, the light-emitting portion including the electrode plate serving as a back electrode; and an antenna disposed in a direction of another surface of the electrode plate, the antenna having a stripline structure or a microstrip line structure and using a potential of the electrode plate as a reference potential.

Abstract: Provided are novel photovoltaic cell alignment apparatuses and methods for fabricating photovoltaic module sub-assemblies that include multiple aligned photovoltaic cells. The apparatuses and methods provide high-speed precise alignment of the cells with respect to each other and other components of a photovoltaic module. In certain embodiments, a set of photovoltaic cells is first aligned on an alignment plate of an alignment apparatus and then transferred to a sealing sheet of the module such that the respective alignments of the cells are maintained during transfer. The alignment plate may include multiple cell receiving areas that have corresponding alignment edges. Aligning photovoltaic cells on this plate may involve forcing the cells against the alignment edges and/or moving the cells in the receiving areas in a direction parallel to the alignment edges.

Abstract: An object is to provide a semiconductor device which achieves miniaturization as well as suppressing a defect. Further, another object is to provide a semiconductor device which achieves miniaturization as well as keeping favorable characteristics. Is provided a semiconductor device including: a source wiring and a drain wiring each of which include a first conductive layer and a second conductive layer having a smaller thickness than the first conductive layer; an insulating layer which has an opening portion and is provided over the source wiring and the drain wiring; an oxide semiconductor layer which is in contact with part of the second conductive layer of the source wiring or the drain wiring in the opening portion; a gate insulating layer provided over the oxide semiconductor layer; and a gate electrode provided over the gate insulating layer.

Abstract: According to one embodiment, an image sensor includes an image-sensing element region formed by arranging a plurality of image-sensing elements on a semiconductor substrate and element isolation portions formed to isolate the image-sensing elements, and a logic circuit region formed in a region different from the image-sensing element region on the substrate and including a plurality of gate patterns. Further, dummy element isolation portions are arranged with a constant pitch in the boundary region between the image-sensing element region and the logic circuit region.

Abstract: According to one embodiment, an image sensor includes an image-sensing element region formed by arranging a plurality of image-sensing elements on a semiconductor substrate, and a logic circuit region formed in a region different from the image-sensing element region on the substrate and including a plurality of gate patterns. Further, dummy gate patterns are formed with a constant pitch on the image-sensing element region.

Abstract: a method for producing a semiconductor device provided in such a manner that a first layer and a second layer are laminated to ensure that their TSVs are arranged in almost a straight line, including: first layer production steps including steps of preparing a substrate, forming a transistor of an input/output circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; second layer production steps including steps of preparing a substrate, forming a transistor of a logic circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; a connection step of connecting surfaces of the first layer and the second layer on a side opposite to substrates of the first layer and the second layer to ensure that the TSV of the first layer and the TSV of the second layer are arranged in almost a straight line; and a step of removing the substrate of the

Abstract: An image sensor such as a backside illumination image sensor may be provided with analog circuitry, digital circuitry, and an image pixel array on a semiconductor substrate. Trench isolation structures may separate the analog circuitry from the digital circuitry on the substrate. The trench isolation structures may be formed from dielectric-filled trenches in the substrate that isolate the portion of the substrate having the analog circuitry from the portion of the substrate having the digital circuitry. The trench isolation structures may prevent digital circuit operations such as switching operations from negatively affecting the performance of the analog circuitry. Additional trench isolation structures may be interposed between portions of the substrate on which bond pads are formed and other portions of the substrate to prevent capacitive coupling between the bond pad structures and the substrate, thereby enhancing the high frequency operations of the image sensor.

Abstract: A solar module having a plurality of series connected pn junction production solar cells, where at least one bypass diode (2) is provided with a surface area adapted to dissipate heat generated from one or more of the series connected production cells. A substantial part of the surface area is disposed substantially flush with the front and/or rear face of a production cell. The bypass diode (2) is electrically connected in parallel and with opposite polarity to at least one production cell (1) by electrical conductors (3).

Abstract: An integrated circuit structure includes an interconnect structure that includes a plurality of metal layers, wherein the interconnect structure is under a semiconductor substrate. A metal pad is formed in one of the plurality of metal layers. A dielectric pad extends from a bottom surface of the semiconductor substrate up into the semiconductor substrate. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate and the dielectric pad. An edge of the semiconductor substrate in the opening is vertically aligned to an edge of the dielectric pad in the opening. The opening stops on a top surface of the metal pad. A dielectric spacer is disposed in the opening, wherein the dielectric spacer is formed on the edge of the semiconductor substrate and the edge of the dielectric pad.

Abstract: Image sensor arrays may include bulk-charge-modulated-device (BCMD) sensor pixels. The BCMD sensor pixels may be used in back-side-illuminated (BSI) image sensors. A BCMD sensor pixel need not include a dedicated addressing transistor. The BCMD sensor pixel may include a gated drain reset (GDR) structure that is used to perform reset operations. The GDR structure may be shared among multiple pixels, which provides increased charge storage capacity for high resolution image sensors. A negative back body bias may be applied to the BCMD pixel array, allowing the depletion region under each BCMD pixel to extend all the way to the back silicon surface. Extending the depletion region by negatively biasing the back silicon surface may serve to minimize pixel crosstalk.

Abstract: In a photoelectric conversion apparatus including charge storing portions in its imaging region, isolation regions for the charge storing portions include first isolation portion each having a PN junction, and second isolation portions each having an insulator. A second isolation portion is arranged between a charge storing portion and at least a part of a plurality of transistors.

Abstract: A method for manufacturing a display panel includes; formation of a lower gate line, disposal of a semiconductor on the lower gate line, disposal of a lower data line substantially perpendicular to the lower gate line, disposal of an insulating layer having a plurality of trenches exposing the lower gate line and the lower data line on the lower data line, disposal of an upper gate line directly on the lower gate line and within the plurality of trenches, and disposal of an upper data line directly on the lower data line and within the plurality of trenches.

Abstract: According to one embodiment, an information recording and reproducing device includes a stacked body. The stacked body includes a first layer, a second layer and a recording layer provided between the first layer and the second layer. The recording layer includes a phase-change material and a crystal nucleus. The phase-change material is capable of reversely changing between a crystal state and an amorphous state by a current supplied via the first layer and the second layer. The crystal nucleus is provided in contact with the phase-change material and includes a crystal nucleus material having a crystal structure identical to a crystal structure of the crystal state of the phase-change material, and a crystal nucleus coating provided on a surface of the crystal nucleus material and having a composition different from a composition of the crystal nucleus material.

Abstract: A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

Abstract: Provided is a method of manufacturing a semiconductor device which can form a high-performance photodiode in which variation in output characteristics and performance deterioration are suppressed. A prescribed gate metal is used to form a shield section 34a that covers a portion of a first semiconductor layer 30a for a photodiode that becomes an intrinsic semiconductor region on a gate insulating film 29 and to form first to fourth gate electrodes 34b to 34e that cover portions of respective second to fifth semiconductor layers 30b to 30e for thin film transistors that become channel regions on the gate insulating film 29. Then, using the shield section 34a as a mask, an n-type region and p-type region are formed in the first semiconductor layer 30a. Then, the shield section 34a is removed.

Abstract: A circuit board (1) includes a plurality of transistor elements on an insulating substrate (2). At least one of the plurality of transistor elements is an oxide TFT (10) including, as a channel layer (11), an oxide semiconductor. At least one of the plurality of transistor elements is an a-SiTFT (20) (i) being different from the oxide TFT (10) in functions as circuit components and (ii) including, as a channel layer (21), an amorphous silicon semiconductor. The oxide TFT (10) is a top gate transistor, and the a-SiTFT (20) is a bottom gate transistor. This provides: a configuration that can (a) enhance the performance of the circuit board equipped with the TFTs differing in their respective functions as circuit components and (b) reduce the area necessary for mounting the TFTs; and a method for producing the circuit board.

Abstract: A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight A CMOS active pixel image sensor includes a plurality of pinned photodiode photodetectors that use a common output transistor. In one configuration, the charge from two or more pinned photodiodes may be binned together and applied to the gate of an output transistor.