Abstract: The disclosure provides a transparent display device including an exposed region and a non-exposed region. The non-exposed region is adapted for being hidden by a frame. The transparent display device includes a plurality of pixels and a driving element. The pixels are disposed in the exposed region. The driving element is adapted for driving the pixels, the driving element is disposed in the non-exposed region, and the non-exposed region partially surrounds the exposed region.

Abstract: Techniques for tight pitch patterning are provided. In one aspect, a patterning method includes: forming mandrels on a substrate; forming spacers that are undoped alongside the mandrels, wherein gaps are present between the spacers; filling the gaps with a sacrificial material having a dopant; forming a mask having an opening marking a cut region of at least one of the spacers; removing the sacrificial material from the cut region of the at least one spacer via the mask; removing the mask; performing an anneal to diffuse the dopant from the sacrificial material into the spacers to form doped spacers, wherein following the anneal the cut region of the at least one spacer remains undoped; removing the cut region of the at least one spacer selective to the doped spacers; and patterning features in the substrate using the doped spacers as a hardmask. A patterning structure is also provided.

Abstract: A laminate and a method for producing a patterned substrate using the same are disclosed herein. In some embodiments, a laminate includes a substrate, and a stripe pattern having first and second polymer lines alternately and repeatedly disposed on the substrate, wherein the first polymer line comprises a first polymer having a first polymerized unit having a ring structure connected to a main chain and a second polymerized unit represented by Formula 1. The method may be applied to manufacture of devices, such as electronic devices, or of applications, such as integrated optical systems, guidance and detection patterns of magnetic domain memories, flat panel displays, liquid crystal displays (LCDs), thin film magnetic heads or organic light emitting diodes, and may be used to build a pattern on a surface used in manufacture of discrete track media, such as integrated circuits, bit-patterned media and/or magnetic storage devices such as hard drives.

Abstract: A system and method provides a more precise mole delivery amount of a process gas, for each pulse of a pulse gas delivery, by measuring a concentration of the process gas and controlling the amount of gas mixture delivered in a pulse of gas flow based on the received concentration of the process gas. The control of mole delivery amount for each pulse can be achieved by adjusting flow setpoint, pulse duration, or both.

Abstract: A semiconductor substrate has an exposed surface having a compositionally uniform metal, and an embedded surface having the metal and an oxide. The exposed surface is polished using a first slurry including a first abrasive and a first amine-based alkaline until the embedded surface is exposed. The embedded surface is polished using a second slurry including a second abrasive and a second amine-based alkaline. The second abrasive is different from the first abrasive. The second amine-based alkaline is different from the first amine-based alkaline. The metal and the oxide each has a first and a second removal rate in the first slurry, respectively, and a third and fourth removal rate in the second slurry, respectively. A ratio of the first removal rate to the second removal rate is greater than 30:1, and a ratio of the third removal rate to the fourth removal rate is about 1:0.5 to about 1:2.

Abstract: An assembly for producing energy may include a fuel cell, a fluidic cell circuit configured to receive a first heat-transfer fluid and arranged at least partially around the fuel cell, a reversible thermodynamic system configured to alternatively: (i) evacuate the thermal energy produced by the fuel cell and transform it into mechanical energy through the first heat-transfer fluid, and (ii) input thermal energy to the fuel cell through the first heat-transfer fluid, wherein the thermodynamic system includes: (a) a fluidic thermodynamic circuit to receive a second heat-transfer fluid; (b) a first exchanger to exchange thermal energy between the fluidic thermodynamic circuit and the fluidic cell circuit; and (c) a second exchanger configured to exchange thermal energy between the fluidic thermodynamic circuit and an external source.

Abstract: An article storage apparatus includes a sensor device sensing gases included in air in a chamber where an article is stored; a concentrator concentrating the gases contained in the air; a filtering device filtering the gases contained in the air; and at least one processor. The at least one processor controls the concentrator to concentrate the gases contained in the air, and identifies a condition of the article based on a concentration level of a target gas related to the article measured by the sensor device when the target gas is extracted as gases desorbed from the concentrator pass the filtering device.

Abstract: An acoustic wave device includes an acoustic wave generator, a support portion, a protective member, and at least one element embedded in the protective member. The acoustic wave generator is disposed on a surface of a substrate. The support portion is disposed on the substrate along a circumference of the acoustic wave generator. The protective member is coupled to the support portion and disposed to be spaced apart from the acoustic wave generator by an interval.

Abstract: An apparatus system is provided which comprises: a substrate; a metal pillar formed on the substrate, the metal pillar comprising a first section and a second section, wherein the first section of the metal pillar is formed by depositing metal in a first opening of a first photoresist layer, and wherein the second section of the metal pillar is formed by depositing metal in a second opening of a second photoresist layer.

Abstract: Apparatus for a multi-source ion beam etching (IBE) system are provided herein. In some embodiments, a multi-source IBE system includes a multi-source lid comprising a multi-source adaptor and a lower chamber adaptor, a plurality of IBE sources coupled to the multi-source adaptor, a rotary shield assembly coupled to a shield motor mechanism configured to rotate the rotary shield, wherein the shield motor mechanism is coupled to a top portion of the multi-source lid, and wherein the rotary shield includes a body that has one IBE source opening formed through the body, and at least one beam conduit that engages the one IBE source opening in the rotary shield on one end, and engages the bottom portion of the IBE sources on the opposite end of the beam conduit.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The method further includes forming a recess in the first film using the second film as a mask. The second film includes a first layer having carbon and a second layer having carbon formed on the first layer. The second layer has a second carbon density lower than a first carbon density of the first layer.

Abstract: An apparatus and method of processing a workpiece is disclosed, where a coating is applied to a workpiece and the workpiece is subsequently subjected to an etching process. These processes are performed by one semiconductor processing apparatus while the workpiece is scanned relative to the apparatus. A precursor is applied to the workpiece by the apparatus. The apparatus then uses plasma, heat or ultraviolet radiation to activate the precursor to form a coating. After the coating is applied, the apparatus is configured to perform the etching process. In certain embodiments, the etching process is a directional etching process.

Abstract: A system for dispensing cryogenic liquid includes a container defining an interior with a partition dividing the interior into primary and reserve chambers. Cryogenic liquid within the primary chamber is separated from cryogenic liquid in the reserve chamber. The partition provides a headspace cornrnurrrcation passage. A primary pressure building circuit has an inlet selectively in liquid communication with the primary chamber and an outlet in fluid communication with the headspaces of the primary and reserve chambers. A reserve pressure building circuit has an inlet selectively in liquid communication with the reserve chamber and an outlet in fluid communication with the headspaces of the primary and reserve chambers. An equalizing circuit is selectively in liquid communication with the primary and reserve chambers. A dispensing line is selectively in liquid communication with the primary chamber.

Abstract: An OLED display substrate, a method of manufacturing the OLED display substrate, and a display device are provided. The OLED display substrate includes a plurality of aperture regions arranged in an array on a base substrate; and a plurality of storage capacitors on the base substrate, an orthographic projection of each storage capacitor of the plurality of storage capacitors on the base substrate having an overlapping region with an orthographic projection of an aperture region corresponding to the storage capacitor in the plurality of aperture regions on the base substrate.

Abstract: A plasma processing apparatus includes a processing chamber in which a wafer 1 is processed by using plasma, a radio-frequency power supply that supplies radio-frequency power for generating the plasma, a sample table 2 which is arranged in the processing chamber and in which the wafer 1 is mounted, and a DC power supply 106 which is electrically connected to the sample table 2 and which causes the sample table 2 to generate a suction force. The sample table 2 includes a protruded portion 201a that sucks the wafer 1 by the suction force and a level different portion 201b protruding from a lower portion of the protruded portion 201a. A ring 5 that can be in contact with a lower surface of the wafer 1 is provided outside the protruded portion 201a. A space portion 7 formed by the wafer 1, the protruded portion 201a, and the ring 5 is sealed in a state in which the wafer 1 is sucked to an upper surface of the protruded portion 201a of the sample table 2.

Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.

Abstract: A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C—SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000° C., to a thickness of at least 0.5 ?m. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.

Abstract: An apparatus for processing a substrate is provided. The apparatus for processing the substrate includes a housing having a process space, a gas supply unit to supply gas into the process space, a support unit including a chuck to support the substrate in the process space and a lower electrode to surround the chuck when viewed from a top, a temperature adjusting plate provided in the housing, a dielectric plate unit coupled to the temperature adjusting plate, and having a dielectric plate disposed in opposite to the substrate supported by the support unit in the process space, and an upper electrode unit coupled to the temperature adjusting plate, and having an upper electrode disposed in opposition to the lower electrode. The dielectric plate unit includes a first base disposed between the dielectric plate and the temperature adjusting plate.

Abstract: Methods for etching features into carbon material using a metal-doped carbon-containing hard mask to reduce and eliminate redeposition of silicon-containing residues are provided herein. Methods involve depositing a metal-doped carbon-containing hard mask over the carbon material prior to etching the carbon material, patterning the metal-doped carbon-containing hard mask, and using the patterned metal-doped carbon-containing hard mask to etch the carbon material such that the use of a silicon-containing mask during etch of the carbon material is eliminated.

Abstract: A method includes forming a dummy gate stack on a top surface and a sidewall of a middle portion of a semiconductor fin, and forming a spacer layer. The spacer layer includes a first portion on a sidewall of the dummy gate stack, and a second portion on a top surface and a sidewall of a portion of the semiconductor fin. The method further includes performing an implantation on the spacer layer. After the implantation, an anneal is performed. After the anneal, the second portion of the spacer layer is etched, wherein the first portion of the spacer layer remains after the etching. A source/drain region is formed on a side of the semiconductor fin.

Abstract: Provided is a lift pin for an epitaxial growth apparatus, which can prevent the back surface of a silicon wafer from being damaged by the lift pin, reduce emission of dust due to the rubbing of the lift pin against the wall surface of a through hole in a susceptor, and prevent peeling of glassy carbon. The lift pin has a straight trunk part to be inserted through the through hole; a head part to be made to abut a silicon wafer; and a cover part covering at least a top of the head part. The straight trunk part and the head part are made of a porous body, the cover part is made of a carbon-based covering material, and at least part of voids of the porous body of the head part is filled with the cover part.

Abstract: A method is described for modifying the mechanical properties of NIL materials. The method includes applying an imprint mask to a nano-imprint lithography (NIL) material layer to create an imprinted NIL material layer, with the NIL material layer comprised of a NIL material. The method further includes detaching the imprinted NIL material layer from the imprint mask, with the modulus level of the NIL material below a flexibility threshold to cause a shape of the imprinted NIL material layer to remain unchanged after detachment. The modulus level of the NIL material of the imprinted NIL material layer is increased beyond a strength threshold to create a first imprint layer, with the imprint layer having a structure that remains unaffected by a subsequent process to form a second imprint layer matching a master mold pattern.

Abstract: The present disclosure provides a self-aligned two-time forming method capable of preventing sidewalls from being deformed, comprises sequentially growing a first silicon nitride layer, a first silicon oxide layer, a titanium nitride layer, a second silicon oxide layer, a second silicon nitride layer and a polysilicon layer on a via layer from bottom to top; defining a pattern by using the polysilicon layer as a hard mask, and etching the second silicon nitride layer to an upper surface of the second silicon oxide layer to form a plurality of silicon nitride pattern structures from the second silicon nitride layer; forming sidewalls on sidewalls of the plurality of silicon nitride pattern structures; removing the silicon nitride pattern structures in the sidewalls; etching the silicon nitride layer and the titanium nitride layer by using the sidewalls as a hard mask to form a titanium nitride pattern structure.

Abstract: A package comprising a carrier, an electronic component mounted on the carrier, and an identifier indicative of an origin of the package and being formed on and/or in the carrier is disclosed.

Abstract: Methods and associated apparatus for reconstructing a free-form geometry of a substrate, the method including: positioning the substrate on a substrate holder configured to retain the substrate under a retaining force that deforms the substrate from its free-form geometry; measuring a height map of the deformed substrate; and reconstructing the free-form geometry of the deformed substrate based on an expected deformation of the substrate by the retaining force and the measured height map.

Abstract: A polishing liquid containing abrasive grains, a hydroxy acid, a polyol, a cationic compound, and a liquid medium, in which a zeta potential of the abrasive grains is positive and a weight average molecular weight of the cationic compound is less than 1000.

Abstract: According to an embodiment of the present disclosure, a method of manufacturing semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer and exposing upper portion of the line-end cut pattern; reducing a width of the line-end cut pattern; etching the spacer layer to expose the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the reduced line-end cut pattern as an etch mask.

Abstract: A method for fabricating a semiconductor device is provided. The method includes the actions of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose a conductive portion in the substrate; forming a dielectric layer on a sidewall of the opening; performing a dry etching process to form a hole in the conductive portion; removing the dielectric layer; and depositing a conductive pattern over the sidewall of the opening and in the hole.

Abstract: An interconnect structure and methods of forming the interconnect structure an interconnect dielectric including at least one contact landing within the interconnect dielectric and/or underlying the interconnect dielectric. The structure and methods include roughening an exposed surface of at least one contact landing to increase the surface area of a conductive metal subsequently disposed in a contact feature and in direct contact with the roughened surface of the least one contact landing.

Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

Abstract: Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate along a vertical direction. In some embodiments, the semiconductor device also includes a marking pattern having a plurality of interleaved layers of different materials over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area, the central marking structure dividing the marking area into a first marking sub-area farther from the stack structure and a second marking sub-area closer to the stack structure, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.

Abstract: An optical transmission device has a modulator, a first terminal groove, and relay groove. The modulator has a groove on a waveguide formed on a substrate. EO polymer is placed in the groove in the modulator. The modulator modulates light propagated through the waveguide by changing the phase of the light propagated through the waveguide through change of the refractive index of the EO polymer placed in the groove in the modulator by means of an electric signal. The first terminal groove is formed on the substrate and has a width larger than a width of the groove in the modulator. The relay groove is formed on the substrate and communicates with the groove in the modulator and the first terminal groove. Furthermore, the EO polymer is placed in the relay groove and the first terminal groove.

Abstract: A process of forming a 3D memory device includes forming a stacked structure with a plurality of stacked layers, etching the stacked structure to form stepped trenches each comprising a plurality of steps, forming a hard mask layer with a plurality of openings over the stepped trenches, forming a photoresist layer over the hard mask layer, and etching through the plurality of openings using the hard mask layer and the photoresist layers as an etch mask to extend a bottom of the stepped trenches to a lower depth.

Abstract: In a an apparatus and a method for manufacturing a stereoscopic shape using a laser and a powder, the apparatus includes a chamber, a powder supplier, a table, a cotter, a first laser head, a first stage, a second laser head and a second stage. The powder supplier provides a predetermined quantity of powder. The powder is sequentially integrated to be a plurality of powder layers in the table. The cotter moves between the powder supplier and the table, and forms the powder to be a predetermined thickness. The first laser head has a first scanner and a first F theta lens, and irradiates a first laser beam to the powder layer. The first stage transfers the first laser head. The second laser head has a second scanner and a second F theta lens, and irradiates a second laser beam. The second stage transfers the second laser head.

Abstract: A method of CMP includes providing a slurry solution including ?1 per-compound oxidizer in a concentration between 0.01 M and 2 M with a pH from 2 to 5 or 8 to 11, and ?1 buffering agent which provides a buffering ratio ?1.5 that compares an amount of a strong acid needed to reduce the pH from 9.0 to 3.0 as compared to an amount of strong acid to change the pH from 9.0 to 3.0 without the buffering agent. The slurry solution is exclusive any hard slurry particles or has only soft slurry particles that have throughout a Vickers hardness <300 Kg/mm2 or Mohs Hardness <4. The slurry solution is dispensed on a hard surface having a Vickers hardness >1,000 kg/mm2 is pressed by a polishing pad with the slurry solution in between while rotating the polishing pad relative to the hard surface.

Abstract: The semiconductor device includes a semiconductor element, a first lead, and a second lead. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a thickness direction. The semiconductor element includes an electron transit layer disposed between the element obverse surface and the element reverse surface and formed of a nitride semiconductor, a first electrode disposed on the element obverse surface, and a second electrode disposed on the element reverse surface and electrically connected to the first electrode. The semiconductor element is mounted on the first lead, and the second electrode is joined to the first lead. The second lead is electrically connected to the first electrode. The semiconductor element is a transistor. The second lead is spaced apart from the first lead and is configured such that a main current to be subjected to switching flows therethrough.

Abstract: Shrinkage and mass losses are reduced in photoresist exposure and post exposure baking by utilizing a small group which will decompose. Alternatively a bulky group which will not decompose or a combination of the small group which will decompose along with the bulky group which will not decompose can be utilized. Additionally, polar functional groups may be utilized in order to reduce the diffusion of reactants through the photoresist.

Abstract: A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer is formed over the semiconductor substrate. A plurality of dopants is formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing of the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion. An underneath layer is patterned to form a hole in the underneath layer using the patterned first semiconductive layer as a mask to pattern. A sidewall profile of the hole in the underneath layer is controlled by the first sidewall profile of the first portion of the first semiconductive layer.

Abstract: Systems and methods for real time semiconductor manufacturing cluster tool health monitoring are provided via an in-situ sensor. In a method embodiment, an operation procedure for pumping/venting load lock (LL), and LL doors facing vacuum transfer module (VTM) and equipment front end module (EFEM), sensor installation location and operation procedure, and data flow and analysis process are provided. The sensor provides real-time data and monitors airborne particle contamination on EFEM, load lock (LL), and VTM, and plurality of process modules (PMs) simultaneously by correlating door open/close time and vent/pump timing in the loadlock to the particle measurement data. The method further provides an operation for determining that a maintenance procedure is recommended on one of the EFEM, the LL, the VTM, or the plurality of PMs based on the real time measurement data, door state data, and using machine learning algorithms.

Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.

Abstract: Compositions and designs are described for a sectional porous carrier used in processing microelectronics where thin device substrates are affixed by adhesive to the carrier and form an impervious bonded stack that is resistant to thermal and chemical products during processing and is easily handled by a substrate handling vacuum robot, and subsequently allows rapid removal (debonding) in batch operations by directional penetration into sectional porous regions by selective liquids which release the carrier from the device wafer without harm. The invention carrier with porous regions is used for temporary support of thin and fragile device substrates having capabilities of selective penetration of chemical liquids to pass through the porous regions, access and breakdown the bonding adhesive, and allow it to release without damage to the device substrate.

Abstract: A distributed feedback laser having a conjugated dendrimer as the active lasing component, and a method for patterning conjugated dendrimers.

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Abstract: A system and method for fabricating an orifice in a multi-layered semiconductor substrate and singulation of the semiconductor substrate includes adding a sacrificial layer of material to a first surface of a semiconductor substrate; subsequently, removing a first radius of a first depth of material from the semiconductor substrate along a direction normal to the first surface, the removal of the first depth of material uses a first removal technique that removes the first depth of material; and removing a second radius of a second depth of material from the semiconductor substrate along the direction normal to the first surface based on the removal of the first depth of material, the removal of the second depth of material uses a second removal technique.

Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.

Abstract: Fabrication methods and resulting structures for single and double diffusion breaks are provided. Aspects include forming one or more fins on a substrate, the substrate including a first region and a second region, forming a plurality of sacrificial gate structures over channel regions associated with the one or more fins, forming a single diffusion break cavity in the first region of the substrate, forming a double diffusion break cavity in the second region of the substrate, depositing a first dielectric material in the single diffusion break cavity, and depositing a second dielectric material in the double diffusion break cavity.

Abstract: Particularly provided is a method and a system for screening nanoparticles which allow effective search of conditions for surface modification of nanoparticles and reduction in the time, the labor, and the amount of a sample required for the surface modification compared with conventional techniques. The method for screening nanoparticles includes the steps of: dividing a nanoparticle suspension for a respective plurality of containers provided in a containment receptacle; performing surface modification on nanoparticles under different conditions for the respective containers; preparing evaluation samples by adding a dispersion medium into each container and mixing the nanoparticles and the dispersion medium; and performing evaluation on the evaluation sample in each container by optical analysis.

Abstract: Disclosed is a method for cleaning a photo mask. The method includes a pre-treatment operation of wetting a chemical on an entire surface of the photo mask in a state in which the photo mask is stopped, and a cleaning operation of supplying the chemical to a pattern area of the photo mask in a state in which the photo mask is rotated.

Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.