Abstract: High performance, high bandgap, lattice-mismatched, photovoltaic cells (10), both transparent and non-transparent to sub-bandgap light, are provided as devices for use alone or in combination with other cells in split spectrum apparatus or other applications.

Abstract: Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.

Abstract: An image forming apparatus includes image carriers; an exposing unit that forms latent images on the image carriers; a developing unit that develops the latent images with toners of different colors from each other; a first transfer unit that forms a color image by superimposing and transferring the developed images onto a second image carrier; a test pattern forming unit that forms, on the image carriers, test patterns to be transferred onto the second image carrier; and test pattern detection units capable of detecting the test patterns transferred onto the second image carrier in different positions from each other in a main-scanning direction. The test pattern forming unit selectively switches, depending on a width of the test patterns in the main-scanning direction, whether to form each of the test patterns in a position detectable by the corresponding one of the test pattern detection units.

Abstract: Provided is a photo active layer for a solar cell or a light emitting diode and a fabricating method thereof. The photo active layer is formed by alternately stacking silicon quantum dot layers in which a plurality of silicon quantum dots containing conductive type impurities are formed in a medium, which is a silicon compound, and conductive layers, which are polycrystalline silicon layers, containing the same conductive type impurities as those of the silicon quantum dots.

Abstract: A three-dimensional (3D) light-emitting device may include a plurality of 3D light-emitting structures formed apart from one another, each 3D light-emitting structure including: a semiconductor core vertically grown on one surface and doped in a first conductive type; an active layer formed so as to surround a surface of the semiconductor core; and a first semiconductor layer formed so as to surround a surface of the active layer and doped in a second conductive type. The 3D light-emitting device may include: a first porous insulating layer formed between lower corner portions of the 3D light-emitting structures so as to expose upper end portions of the 3D light-emitting structures; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the semiconductor core.

Abstract: A thin-film transistor, method of manufacturing the same, and organic light-emitting diode (OLED) display including the same are disclosed. In one aspect, the thin-film transistor includes an active layer including a channel region, a source region, and a drain region, wherein the active layer has a top surface. The transistor also includes a gate insulating layer formed over the active layer and a gate metal layer formed over the gate insulating layer and having a bottom surface. The area of the bottom surface of the gate metal layer is less than the area of the top surface of the active layer and the bottom surface of the gate metal layer overlaps the top surface of the active layer.

Abstract: Embodiments of the present disclosure relate generally to a method of passivating and/or removing oxides on a semiconductor surface by using ammonium sulfide, the ammonium sulfide is formed by reacting ammonia and hydrogen sulfide in a semiconductor processing chamber, therefore the ammonium sulfide can be used to clean and remove oxides on a semiconductor surface without the concern of ESH and storage, the ammonium sulfide can also be used to passivate a semiconductor surface by forming a layer of sulfur, and thus preventing the reformation of native oxides, the layer of sulfur can be optionally removed to reduce the thickness of the semiconductor material.

Abstract: A stack is formed over a substrate, which comprises an alternating plurality of first material layers including a first material and second material layers including a second material. A patterned hard mask is formed, which includes multiple laterally spaced apart strips. A trimming material layer is formed over the hard mask layer. At least one cycle of process steps is subsequent performed, which include etching the first material employing the second material and the trimming material layer as an etch mask, trimming the trimming material layer to expose a strip of the hard mask layer, etching the second material and the exposed strip of the hard mask layer employing the trimming material layer as an etch mask, and trimming the trimming material layer to expose an edge of a next strip of the hard mask layer. Stepped surfaces suitable for formation of contact via array can thus be formed.

Abstract: Methods of producing layers of patterned graphene with smooth edges are provided. The methods comprise the steps of fabricating a layer of crystalline graphene on a surface, wherein the layer of crystalline graphene has a crystallographically disordered edge, and decreasing the crystallographic disorder of the edge of the layer of crystalline graphene by heating the layer of crystalline graphene on the surface at an elevated temperature in a catalytic environment comprising carbon-containing molecules.

Abstract: A light-emitting diode (LED) includes a first type semiconductor layer, a second type semiconductor layer, a first current controlling structure, and a first electrode. The second type semiconductor layer is joined with the first type semiconductor layer. The second type semiconductor layer has a first region and a second region, in which the first region has a first threading dislocation density, the second region has a second threading dislocation density, and the first threading dislocation density is greater than the second threading dislocation density. The first current controlling structure is joined with the first type semiconductor layer and has at least one first current-injecting zone therein, in which the vertical projection of the second region on the first current controlling structure at least partially overlaps with the first current-injecting zone. The first electrode is electrically coupled with the first type semiconductor layer.

Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.

Abstract: Exemplary embodiments of the present invention provide a substrate recycling method and a recycled substrate. The method includes separating a substrate having a first surface from an epitaxial layer, performing a first etching of the first surface using electrochemical etching, and performing, after the first etching, a second etching of the first surface using chemical etching, dry etching, or performing, after the first etching, chemical mechanical polishing of the first surface.

Abstract: A method for manufacturing a light transmissive optical component, includes a first etching process of forming a depressed portion by applying etching to a silicon region of a plate-shaped member, a thermal oxidation process of forming a silicon oxide film by thermally oxidizing an inner side surface of the depressed portion, and a nitride film formation process of forming a silicon nitride film that covers the silicon oxide film. Accordingly, it is possible to realize a manufacturing method for an optical component which is capable of uniformly forming a silicon oxide film on a semi-transmissive reflecting surface which is largely inclined (or nearly vertical) with respect to a substrate surface, and an optical component produced by this method.

Abstract: A robot system includes: a robot including a hand configured to hold a thin plate-shaped workpiece and an arm configured to move the hand; and a robot controller configured to control the robot. The robot controller controls the robot to perform a transfer of the workpiece at a predetermined workpiece transfer position in such a way that the hand is moved in a horizontal direction while being moved in a vertical direction after the hand has reached the workpiece transfer position.

Abstract: A method of manufacturing a semiconductor device includes: forming an etching mask layer on a semiconductor substrate having an etching target layer, patterning the etching mask layer to form a plurality of etching mask patterns, and forming a subsidiary layer surrounding the etching mask patterns having a uniform critical dimension and gap to form hard mask patterns including the subsidiary layer and the etching mask patterns.

Abstract: The present invention provides a polishing slurry capable of polishing even high-hardness materials such as silicon carbide and gallium nitride at a high polishing speed. The present invention is a polishing slurry including a slurry containing a manganese oxide particle and a manganate ion for polishing high-hardness materials having a Mohs hardness of 8 or higher. In the present invention, the manganese oxide particle in the slurry is preferably 1.0 mass % or more; the manganese oxide is preferably manganese dioxide; and the manganate ion is preferably permanganate ion. The polishing slurry according to the present invention enables even high-hardness hardly-machinable materials such as silicon carbide and gallium nitride to be polished smoothly at a high speed.

Abstract: Provided is a self-supporting gallium nitride substrate useful as an alternative material for a gallium nitride single crystal substrate, which is inexpensive and also suitable for having a large area. This substrate is composed of a plate composed of gallium nitride-based single crystal grains, wherein the plate has a single crystal structure in the approximately normal direction. This substrate can be manufactured by a method comprising providing an oriented polycrystalline sintered body; forming a seed crystal layer composed of gallium nitride on the sintered body so that the seed crystal layer has crystal orientation mostly in conformity with the crystal orientation of the sintered body; forming a layer with a thickness of 20 ?m or greater composed of gallium nitride-based crystals on the seed crystal layer so that the layer has crystal orientation mostly in conformity with crystal orientation of the seed crystal layer; and removing the sintered body.

Abstract: A trench isolation structure is formed beneath a topmost surface of a semiconductor substrate. A mandrel structure having a bottommost surface that straddles a sidewall edge of the underlying trench isolation structure is then formed. Nitride spacers are formed on sidewalls of the mandrel structure and thereafter the mandrel structure is removed. A dielectric oxide material is then formed having a topmost surface that is coplanar with a topmost surface of each remaining nitride spacer. Each nitride spacer is removed and thereafter a semiconductor fin is epitaxially grown within a cavity in the dielectric oxide material which exposes a topmost surface of the semiconductor substrate.

Abstract: A transistor having a multi-layer structure of oxide semiconductor layers is provided in which a second oxide semiconductor layer having a crystalline structure including indium zinc oxide is formed over a first oxide semiconductor layer having an amorphous structure, and at least a third oxide semiconductor layer is formed stacked over the second oxide semiconductor layer. The second oxide semiconductor layer mainly serves as a carrier path for the transistor. The first oxide semiconductor layer and the third oxide semiconductor layer each serve as a barrier layer for suppressing entrance of impurity states of an insulating layer in contact with the multi-layer structure to the carrier path.

Abstract: An embodiment 3DIC device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a dielectric layer over the semiconductor substrate. The die is disposed over and bonded to the semiconductor chip. The polymer is molded onto the semiconductor chip and the die. The polymer includes a portion level with the dielectric layer, wherein the portion of the polymer comprises a second edge vertically aligned to the first edge of the semiconductor substrate and a third edge contacting the dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer.

Abstract: A method of forming a polycrystalline diamond compact from_a substantially homogeneous suspension of nanodiamond particles and microdiamond particles is disclosed The method includes disposing a first functional group on a plurality of nanodiamond particles to form derivatized nanodiamond particles, and combining the derivatized nanodiamond particles with a plurality of microdiamond particles, metal solvent-catalyst particles and a solvent to form a substantially homogeneous suspension of these particles in the solvent. A method of making an article is also disclosed. The method includes forming a superabrasive polycrystalline diamond compact by combining: a plurality of derivatized nanodiamond particles, a plurality of derivatized microdiamond particles having an average particle size greater than that of the derivatized nanodiamond particles, and a metal solvent-catalyst.

Abstract: Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

Abstract: Disclosed are a method to fabricate a semiconductor device having a two-layered gate structure, and so fabricated a semiconductor. The gate threshold voltage can be tuned by using two metal layers with different workfunctions, disposed over a fin structure on a substrate and extending in parallel to the current flow direction in the fin structure, and by varying individual thicknesses of the layer so as to change the relative coverage of the fin structure by the layers. The method may comprise providing a substrate having a fin structure, depositing first and second gate metals, and forming a gate dielectric layer. The method may further comprise determining the workfunctions of the first and second gate metals and their thicknesses to achieve a desired gate threshold voltage. Forming the first and second gate metal layers and the dielectric layer may use processes such as deposition, epitaxial growth, CMP, or selective etching.

Abstract: Provided is a hetero-substrate that may include a base substrate, a buffer layer disposed on the base substrate, and a first semiconductor layer disposed on the buffer layer, the first semiconductor layer including a nitride semiconductor. A defect blocking layer is disposed on the first semiconductor layer. The defect blocking layer may include a plurality of metal droplets. A second semiconductor layer may be disposed on the defect blocking layer, the second semiconductor layer including a nitride semiconductor.

Abstract: A resist underlayer film forming composition including: a polymer having any one or more repeating structural units of Formulas (1a), (1b), and (1c): two R1s are each independently alkyl group, alkenyl group, aromatic hydrocarbon group, halogen atom, nitro group, or an amino group, two R2s are each independently hydrogen atom, alkyl group, alkenyl group, acetal group, acyl group, or glycidyl group, R3 is aromatic hydrocarbon group optionally having a substituent, R4 is hydrogen atom, phenyl group, or naphthyl group, in (1b), groups of two R3s and atoms or groups of two R4s are optionally different from each other, two “k”s are each independently 0 or 1, m is integer of 3 to 500, n, n1, and n2 are an integer of 2 to 500, p is integer of 3 to 500, X is a single bond or hetero atom, and two Qs are each independently a structural unit; and solvent.

Abstract: A method is described for manufacturing a micromechanical structure, in which a structured surface is created in a substrate by an etching method in a first method step, and residues are at least partially removed from the structured surface in a second method step. In the second method step, an ambient pressure for the substrate which is lower than 60 Pa is set and a substrate temperature which is higher than 150° C. is set.

Abstract: A method is provided for fabricating cross-coupled line segments for use, for instance, as a hard mask in fabricating cross-coupled gates of two or more transistors. Fabricating the structure includes: providing a sacrificial mandrel on the substrate, the sacrificial mandrel including a transverse gap through the mandrel separating the sacrificial mandrel into a first mandrel portion and a second mandrel portion; providing a sidewall spacer along sidewalls of the sacrificial mandrel, where sidewall spacers along sidewalls of the first mandrel portion and the second mandrel portion merge within the transverse gap and form a crossbar; and removing the sacrificial mandrel and selectively cutting the sidewall spacers to define the cross-coupled line segments from the sidewall spacers and crossbar. The transverse gap may be provided by directly printing the first and second mandrel portions spaced apart, or by cutting the sacrificial mandrel to provide the gap.

Abstract: A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars.

Abstract: Sometimes to warp a group III nitride semiconductor and a silicon by the stress of the group III nitride semiconductor acting on the silicon. A semiconductor device includes a substrate, a buffer layer, and a semiconductor layer. A trench is formed on a sixth face of the semiconductor layer. The trench passes through the semiconductor layer and the buffer layer. The bottom of the trench reaches at least the inside of the substrate.

Abstract: A photodiode and the like capable of preventing the responsivity on the short wavelength side from deteriorating while totally improving the responsivity in a type II MQW structure, is provided. The photodiode is formed on a group III-V compound semiconductor substrate, and includes a pixel. The photodiode includes an absorption layer of a type II MQW structure, which is located on the substrate. The MQW structure includes fifty or more pairs of two different types of group III-V compound semiconductor layers. The thickness of one of the two different types of group III-V compound semiconductor layers, which layer has a higher potential of a valence band, is thinner than the thickness of the other layer.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess cavity is formed in the substrate adjacent to the gate stack. A first epitaxial (epi) material is then formed in the recess cavity. A second epi material is formed over the first epi material. A portion of the second epi material is removed by a removing process. The disclosed method provides an improved method by providing a second epi material and the removing process for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.

Abstract: Exemplary embodiments of the present invention disclose a method of fabricating a gallium nitride (GaN) based semiconductor device. The method includes growing GaN based semiconductor layers on a first surface of a GaN substrate to form a semiconductor stack, and separating at least a first portion of the GaN substrate from the semiconductor stack using a wire cutting technique.

Abstract: A linear-shaped core structure of a first material is formed on an underlying material. A layer of a second material is conformally deposited over the linear-shaped core structure and exposed portions of the underlying material. The layer of the second material is etched so as to leave a filament of the second material on each sidewall of the linear-shaped core structure, and so as to remove the second material from the underlying material. The linear-shaped core structure of the first material is removed so as to leave each filament of the second material on the underlying material. Each filament of the second material provides a mask for etching the underlying material. Each filament of the second material can be selectively etched further to adjust its size, and to correspondingly adjust a size of a feature to be formed in the underlying material.

Abstract: A method includes: etching a target layer of a target object in a processing chamber by generating a plasma of a first gas containing at least one of SF6, ClF3 and F2 supplied into the processing chamber to; and forming a protective film on the target layer by generating a plasma of a second gas containing at least one of hydrocarbon, fluorocarbon, and fluorohydrocarbon supplied into the processing chamber. In the etching, a pressure in the processing chamber is set to a first pressure and a first bias power is applied to a lower electrode. In the forming, the pressure is set to a second pressure lower than the first pressure and a second bias power higher than the first bias power is applied to the lower electrode.

Abstract: A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.

Abstract: The present application relates to methods for depositing a smooth, germanium rich epitaxial film by introducing silylgermane as a source gas into a reactor at low temperatures. The epitaxial film can be strained and serve as an active layer, or relaxed and serve as a buffer layer. In addition to the silylgermane gas, a diluent is provided to modulate the percentage of germanium in a deposited germanium-containing film by varying the ratio of the silylgermane gas and the diluent. The ratios can be controlled by way of dilution levels in silylgermane storage containers and/or separate flow, and are selected to result in germanium concentration greater than 55 atomic % in deposited epitaxial silicon germanium films. The diluent can include a reducing gas such as hydrogen gas or an inert gas such as nitrogen gas. Reaction chambers are configured to introduce silylgermane and the diluent to deposit the silicon germanium epitaxial films.

Abstract: An electronic system includes an electronic device of through-hole mounting type comprising an insulating body for embedding at least a chip on which electronic components are integrated, a plurality of conductive leads projecting from the insulating body for said mounting, and a dissipation plate exposed from the insulating body for transferring heat from said electronic component in operation towards the outside of the insulating body. The electronic system includes a heat sink in contact with said dissipation plate for dissipating said heat. The heat sink comprises a first dissipation element, a second dissipation element, and clamping means for clamping the first dissipation element and the second dissipation element together against the insulating body of said electronic device.

Abstract: According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.

Abstract: Provided is a liquid processing apparatus that selectively supplies processing liquids with a switching operation to the surface of a substrate to perform a liquid processing. The liquid processing apparatus includes a first processing liquid supply unit including a first nozzle block that selectively supplies an acidic chemical liquid and a rinse liquid, and a second processing liquid supply unit including a second nozzle block that selectively supplies an alkaline chemical liquid and a rinse liquid. When a chemical liquid is supplied to the substrate from one of the first and second nozzle blocks, the other of the first and second nozzle blocks is retreated to a retreat position. When the rinse liquid is supplied to the substrate from one of the first and second nozzle blocks, the other of the first and second nozzle blocks is moved to a processing position.

Abstract: A barrel-plating quad flat no-lead (QFN) package structure and a method for manufacturing the same. The method includes: providing a metal substrate for a plurality of QFN components; forming a first photoresist film on a top surface of the substrate; forming a plating pattern in the first photoresist film; forming a first metal layer containing a plurality of inner leads; etching the substrate from the back surface of the substrate to form a plurality of I/O pads; filling sealant in the etched areas; attaching at least one die in a predetermined region on the top surface of the substrate; connecting the die and the inner leads using metal wires; sealing the die, the inner leads, and the metal wires with a molding compound; separating the resulting joint QFN components into individual QFN components; and forming a second metal layer on the back surface of the I/O pads.

Abstract: Semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a first pattern in a hard mask using a first lithography process, and forming a second pattern in the hard mask using a second lithography process. A protective layer is formed over the hard mask. Portions of the hard mask and portions of the protective layer are altered using a self-aligned double patterning (SADP) method.

Abstract: An integrated circuit structure includes a passivation layer, a polymer layer over the passivation layer, and a PPI monitor structure. The PPI monitor structure includes a portion overlying a portion of the polymer layer. The PPI monitor structure is electrically floating.

Abstract: A method for fabricating a thin film transistor includes printing source, drain and channel regions on a passivated transparent substrate, forming a gate dielectric over the channel region and forming a gate conductor over the gate dielectric. A permanent antireflective coating is deposited over the source region, drain region and gate electrode, and an interlevel dielectric layer is formed over the permanent antireflective coating. Openings in the permanent antireflective coating and the interlevel dielectric layer are formed to provide contact holes to the source region, drain region and gate electrode. A conductor is deposited in the contact holes to electrically connect to the source region, drain region and gate electrode. Thin film transistor devices and other methods are also disclosed.

Abstract: A clam shell wafer holder includes a base and a lid pivotally connected with the base by an integral hinge. The base includes a rotatable wafer support, and the lid includes a universal frame and a pin holder attachment spaced inwardly from the frame. Only two contact pins are formed in a wafer-facing surface of the pin holder attachment. The contact pins are manually aligned with and contact two points on a wafer when the lid is closed against the base. A method for holding a wafer for plating is provided using the disclosed holder apparatus.

Abstract: A chip package is described which includes a first chip having a first surface and first sides having a first side-wall angle, and a second chip having a second surface and second sides having a second side-wall angle, which faces and is mechanically coupled to the first chip. The chip package is fabricated using a batch process, and the chips in the chip package were singulated from their respective wafers after the chip package is assembled. This is accomplished by etching the first and second side-wall angles and thinning the wafer thicknesses prior to assembling the chip package. For example, the first and/or the second side walls can be fabricated using wet etching or dry etching. Therefore, the first and/or the second side-wall angles may be other than vertical or approximately vertical.

Abstract: Embodiments of the invention are described that use a thin metallic hard mask, which can be a bi-layer film, to increase the incident IBE angle for MTJ sidewall cleaning without losing the process margin for the subsequent interconnection process. The patterned metallic hard mask pads also serve as the top electrode for the MTJ cells. Using a thin metallic hard mask is possible when the hard mask material acts as a CMP stopper without substantial loss of thickness. In the first embodiment, the single layer hard mask is preferably ruthenium. In the second embodiment, the lower layer of the bi-layer hard mask is preferably ruthenium. The wafer is preferably rotated during the IBE process for uniform etching. A capping layer under the hard mask is preferably used as the etch stopper during hard mask etch process in order not to damage or etch through the upper magnetic layer.

Abstract: One embodiment for forming a shaped substrate for an electronic device can form a shaped perimeter to define the substrate shape on the surface of a substrate. The shaped perimeter can extend at least part way into the substrate. A subsequent thinning process can remove substrate material and expose the shaped perimeter effectively forming shaped dies from the substrate.

Abstract: According to example embodiments, a graphene switching devices having a tunable barrier includes a semiconductor substrate that includes a first well doped with an impurity, a first electrode on a first area of the semiconductor substrate, an insulation layer on a second area of the semiconductor substrate, a graphene layer on the insulation layer and extending onto the semiconductor substrate toward the first electrode, a second electrode on the graphene layer and insulation layer, a gate insulation layer on the graphene layer, and a gate electrode on the gate insulation layer. The first area and the second area of the semiconductor substrate may be spaced apart from each other. The graphene layer is spaced apart from the first electrode. A lower portion of the graphene layer may contact the first well. The first well is configured to form an energy barrier between the graphene layer and the first electrode.

Abstract: Provided is a polishing slurry composition, including a non-ionic surfactant represented by the following formula (1) R—(OCH2CH2)x—OH??formula (1) wherein x is an integer from 1 to 50, and R is selected from a group consisting of a C3-C50 alkyl group, a C6-C55 benzylalkyl group and a C6-C55 phenylalkyl group.

Abstract: A method of forming a semiconductor device including providing a functional gate structure on a channel portion of a semiconductor substrate. A gate sidewall spacer is adjacent to the functional gate structure and an interlevel dielectric layer is present adjacent to the gate sidewall spacer. The upper surface of the gate conductor is recessed relative to the interlevel dielectric layer. A multi-layered cap is formed a recessed surface of the gate structure, wherein at least one layer of the multi-layered cap includes a high-k dielectric material and is present on a sidewall of the gate sidewall spacer at an upper surface of the functional gate structure. Via openings are etched through the interlevel dielectric layer selectively to at least the high-k dielectric material of the multi-layered cap, wherein at least the high-k dielectric material protects a sidewall of the gate conductor.