Abstract: To increase the on-state current of a transistor whose channel is formed in an oxide semiconductor layer. To provide a transistor where a resistance-reducing element is introduced into a region of an oxide semiconductor layer which overlaps with part of a source or drain or part of a gate. For example, the thickness of a region of a conductive layer serving as a source or drain or a gate (at least part of a region overlapping with an oxide semiconductor layer) is made smaller than that of the other region of the conductive layer. A resistance-reducing element is introduced into the oxide semiconductor layer through the conductive layer thinned partly, thereby obtaining the oxide semiconductor layer where the resistance-reducing element is introduced into the region overlapping with part of the source or drain or part of the gate. Thus, the on-state current of the transistor can be increased.

Abstract: In some examples, a method includes forming a photoresist layer on a surface of a metallic substrate and developing the photoresist layer to define a pattern exposing a portion of the surface of the metallic substrate. The method also may include forming an electrically conductive layer on a surface of the photoresist layer and the exposed portions of the surface of the metallic substrate. The electrically conductive layer contacts the exposed portions of the surface of the metallic substrate. The method may further include submerging the substrate, the photoresist layer, and the electrically conductive layer in an electrolyte solution; and applying a voltage to between a cathode and an anode submerged in the electrolyte solution to anisotropically etch the metallic substrate where the electrically conductive layer contacts the exposed portions of the surface of the metallic substrate to form at least one feature in the metallic substrate.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The semiconductor device structure further includes a spacer element over a sidewall of the gate stack. The spacer element includes a first layer and a second layer over the first layer. The dielectric constant of the first layer is greater than the dielectric constant of the second layer.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

Abstract: A method is disclosed of removing a first material disposed over a second material adjacent to a field effect transistor gate having a gate sidewall layer that comprises an etch-resistant material on a gate sidewall. The method includes subjecting the first material to a gas cluster ion beam etch process to remove first material adjacent to the gate, and detecting exposure of the second material during the gas cluster ion beam (GCIB) etch process.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten being not less than 30%, patterning the mask layer, and performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the layer to be etched.

Abstract: In a first aspect, the present disclosure provides a method of forming a semiconductor device, including providing an SOI structure comprising a base substrate, a buried insulating material layer formed on the base substrate and an active semiconductor layer formed on the buried insulating structure, forming a germanium-comprising layer on an exposed surface of the active semiconductor layer, forming a trench isolation structure, the trench isolation structure extending through the germanium-comprising layer and the active semiconductor layer, performing an annealing process after the trench isolation structure is formed, the annealing process resulting in an oxide layer disposed on a germanium-comprising active layer which is formed on the buried insulating material layer, and removing the oxide layer for exposing an upper surface of the germanium-comprising active layer.

Abstract: A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include forming trenches in a dielectric layer; filling the trenches with a sacrificial layer; forming and etching a block mask over sacrificial layers to form a cut area over a portion of the trenches; forming spacers at sides of the cut area; removing the sacrificial layer from the portion of the trenches; forming a mask in the cut area and the portion of trenches, the mask selected from a HDP oxide, SiC or SiCNH; selectively etching the spacers; and selectively etching the sacrificial layer and the dielectric layer by RIE to form SAVs.

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: providing a substrate; forming a gate structure on the substrate; forming a recess in the substrate at a lateral side of the gate structure; performing a pre-bake process at a temperature of 740-840° C. and under a pressure of equal to or higher than 150 torr; and forming an epitaxial buffer layer in the recess.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: A method according to an embodiment includes (i) a step of preparing a workpiece in a processing container of a plasma processing apparatus, (ii) a first plasma processing step of generating a plasma of a first processing gas, which contains chlorine, in the processing container, (iii) a second plasma processing step of generating a plasma of a second processing gas, which contains fluorine, in the processing container, and (iv) a third plasma processing step of generating a plasma of a third processing gas, which contains oxygen, in the processing container. A plurality of sequences, each of which includes the first plasma processing step, the second plasma processing step, and the third plasma processing step, are performed.

Abstract: A photoelectric conversion element of an embodiment includes: a back electrode; a heterojunction-type light absorbing layer on the back electrode, containing Cu, selected from Al, In and Ga, and selected from Se and S, and having a chalcopyrite structure; a transparent electrode on the light absorbing layer, wherein aback electrode side-part of the light absorbing layer is of p-type, and a transparent electrode-side part of the light absorbing layer is of n-type, the light absorbing layer has a part with an average crystal grain size of 1,000 nm to 3,000 nm in the vicinity of the back electrode, and the light absorbing layer has apart with an average crystal grain size of at most 500 nm in the vicinity of the transparent electrode or the light absorbing layer has an amorphous part in the vicinity of the transparent electrode.

Abstract: A synthetic gel for crystal growth, which induces only secondary growth from the surface of a silicalite-1 or zeolite beta seed crystal and cannot induce crystal nucleation in the synthetic gel for crystal growth or on the surface of the seed crystal. The synthetic gel contains fumed silica, tetraethylammonium hydroxide (TEAOH), [(NH4)2SiF6], KOH, and H2O, or contains tetraethylorthosilicate (TEOS), tetraethylammonium hydroxide (TEAOH), hydrogen fluoride, and H2O.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate, wherein each trench of the plurality of first trenches extends downward from the substrate major surface to a first height, and each trench of the plurality of second trenches extends downward from the substrate major surface to a second height greater than the first height. The method includes forming a first isolation structure in each of the plurality of first trenches. The method includes forming a second isolation structure in each of the plurality of second trenches, wherein a difference between a height of the first isolation structure and the first height equals a difference between a height of the second isolation structure and the second height.

Abstract: A method of manufacturing a dual-gate FinFET is provided. The method includes: forming a fin structure on the semiconductor substrate, depositing an oxide layer and planarizing until the top of the fin structure is exposed, depositing a hard mask layer and patterning, preforming a first etch back process to one side of the oxide layer, and then removing the rest of the hard mask layer, preforming a second etch back process to the oxide layers at both sides of the fin structure simultaneously, forming a gate dielectric layer on surface of the fin structure, then depositing gate material on the gate dielectric layer and patterning, removing gate material on top of the fin structure, forming a drive gate and a control gate at two sides of the fin structure respectively; wherein height of the control gate is higher than height of the drive gate.

Abstract: In accordance with one embodiment, a multi-reader can be manufactured so as to be able to read from multiple regions of a storage device contemporaneously during operation. Such a device can be configured, for example, by forming a first wall; forming a second wall; and utilizing the first wall and the second wall to form two adjacent reader stacks.

Abstract: A method of determining the charge of at least one test particle, comprising: applying one of an electric current or a voltage across an aperture connecting two chambers, whereby the chambers are at least partially filled with electrolyte and whereby the at least one test particle is suspended in the electrolyte of at least one of the chambers; measuring the other of the electric current or voltage across the aperture; varying a pressure differential between the two chambers; and determining the charge based on the measurements of the electric current or voltage.

Abstract: A system produces devices that include a semiconductor part and a non-semiconductor part. A front end is configured to receive a semiconductor part and to process the semiconductor part. A back end is configured to receive the processed semiconductor part and to assemble the processed semiconductor part and a non-semiconductor part into a device. A transfer device is configured to automatically handle the semiconductor part in the front end and to automatically transfer the processed semiconductor part to the back end.

Abstract: Disclosed is a method for processing GaN based substrate material for manufacturing light-emitting diodes, lasers, and other types of devices. In various embodiments, a GaN substrate is exposed to nitrogen and hydrogen at a high temperature. This process causes the surface of the GaN substrate to anneal and become smooth. Then other processes, such as growing epitaxial layers over the surface of GaN substrate, can be performed over the smooth surface of the GaN substrate.

Abstract: The present invention provides a phase-shift mask comprising a light shading region which is covered by a light shading pattern and a light transmission region which is not covered by the light shading pattern, the light shading pattern comprises a symmetrical part and an asymmetrical part provided outside the symmetrical part, wherein, an optical blocking unit is provided in a part of the light transmission region outside the symmetrical part away from the asymmetrical part, so that intensity of light transmitted through the part of the light transmission region provided with the optical blocking unit is reduced. During an exposure process using the phase-shift mask of the present invention, the obtained exposure intensity is more uniform.

Abstract: The present invention provides an array substrate and method of repairing broken lines therefor, by forming a via on the organic layer corresponding to each intersection of the gate scan lines and the source-drain data lines, and deposing the second passivation layer in the via to form an aperture, with the vias, a U shape long line can be directly laser welded between the apertures at two ends of a broken line position to recover a connection of the broken gate scan line or the source-drain data line as the gate scan line or the source-drain data line on the substrate of the present invention is broken. The method of repairing saves the process of removing the organic layer with laser and effectively reduces the machine laser loss as removing the organic layer to raise the repair efficiency and the repair success rate. Thus, the display quality of the liquid crystal panel product is promoted.

Abstract: A doped mold film is formed with a dopant concentration gradient in the doped mold film that continuously varies in a thickness direction and a portion of the doped mold film is etched in the thickness direction to form a hole so that an electrode can be formed along an inner wall of the hole. The electrode thus formed includes a first outer wall surface, a second outer wall surface, and a third outer wall surface wherein the first outer wall surface is in contact with a sidewall of an insulating pattern formed on a substrate within a through hole formed in the insulating pattern; the second outer wall surface is in contact with a top surface of the insulating pattern and extends in a lateral direction; the third outer wall surface is spaced apart from the first outer wall surface with the second outer wall surface therebetween; and the third outer wall surface extends on the insulating pattern in a direction away from the substrate.

Abstract: An apparatus for drying a substrate may include a spin chuck, a drying chamber and a drying fluid line. The spin chuck may be configured to support the substrate. The spin chuck may rotate the substrate. The drying chamber may be configured to receive the spin chuck. The drying chamber may have an inlet, an outlet and a vortex exhaust. A drying fluid may be supplied through the inlet into the drying chamber. The drying fluid may be drained through the outlet. A vortex of the drying fluid may be drained through the vortex exhaust. The drying fluid line may be connected to the inlet.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched. The mask layer contains at least one type of a metal, boron, and carbon. The metal is selected from a group including tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium and iridium. A composition ratio of the metal is higher than a composition ratio of the boron and a composition ratio of the carbon. The method includes making a hole or a slit in the layer to be etched by performing a dry etching to the layer to be etched using the mask layer being patterned.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate having an oxide film; performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas to the substrate, supplying a carbon-containing gas to the substrate, and supplying a nitrogen-containing gas to the substrate, or performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas to the substrate and supplying a gas containing carbon and nitrogen to the substrate, or performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas containing carbon to the substrate and supplying a nitrogen-containing gas to the substrate, the oxide film being used as an oxygen source to form a nitride layer containing oxygen and carbon as a seed layer; and forming a nitride film containing no oxygen and carbon as a first film on the seed layer.

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove an exposed silicon oxide portion faster than an exposed silicon nitride portion. The inclusion of the oxygen-containing precursor may suppress the silicon nitride etch rate and result in unprecedented silicon oxide etch selectivity.

Abstract: A method of preparing semiconductor dies from a semiconductor wafer having a plurality of fabrication regions separated by dicing lines on the top side of the wafer, and an adhesive coating on the back side of the wafer, comprises applying a repellent material to the fabrication regions and dicing lines where the adhesive coating is not intended to be printed; applying the adhesive coating to the back side of the wafer; removing the repellent material; and separating the wafer along the dicing lines into individual dies.

Abstract: A method of manufacturing a semiconductor device, including steps of: (a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit disposed thereon; (b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face; (c) dividing the wafer into multiple chip bodies concurrently with or after step (b); (d) bonding multiple reinforcing layers to second main faces of the respective chip bodies after step (c); and (e) removing the support plate after step (d).

Abstract: The present disclosure may provide a semiconductor device having a three-dimensional memory device with improved performance and reliability. The device may include a pipe gate having a pipe channel film embedded in the pipe gate. The device may include source-side channel and drain-side channel films coupled respectively to both ends of the pipe channel film. The device may include interlayer insulation films and conductive patterns alternately stacked and disposed over the pipe gate, the alternately stacked interlayer insulation films and conductive patterns surrounding the source-side channel film and the drain-side channel film. The device may include a slit disposed between the drain-side channel film and the source-side channel film and dividing the alternately stacked interlayer insulation films and conductive patterns into a source-side stack and a drain-side stack, the slit having a round shape at a bottom of the slit adjacent to the pipe gate.

Abstract: A method for producing a monolithic template comprises a Si wafer with a layer of a III/V semiconductor epitaxially applied to its surface. The III/V semiconductor has a lattice constant differing by less than 10% from that of Si. The method includes epitaxially growing a layer of a III/V semiconductor on the surface of the Si wafer at a wafer temperature from 350 to 650° C., a growth rate from 0.1 to 2 ?m/h, and a layer thickness from 1 to 100 nm. A layer of another III/V semiconductor, identical to or different from the previously applied III/V semiconductor, is epitaxially grown on the III/V semiconductor layer at a wafer temperature from 500 to 800° C., a growth rate from 0.1 to 10 ?m/h, and a layer thickness from 10 to 150 nm.

Abstract: A fabrication method of a semiconductor piece includes forming a groove that has a first groove portion, and a second groove portion which is a groove portion formed to communicate with a lower part of the first groove portion and extends toward a lower part at a steeper angle than an angle of the first groove portion, has a shape without an angle portion between the first groove portion and the second groove portion, is positioned on the front side, and is formed by dry etching; affixing a retention member including an adhesive layer to the surface in which the groove on the front side is formed; thinning the substrate from the back side of the substrate in a state in which the retention member is affixed; and removing the retention member from the surface after the thinning.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: The imprint apparatus of the present invention includes a holding unit configured to hold a mold; a particle inspection unit configured to inspect whether or not particle is present on an imprint area, in which the resin pattern is formed, of the substrate; a dispenser configured to apply an uncured resin to the imprint area; a movable unit configured to move the imprint area with respect to the holding unit; and a controller. The movable unit is capable of moving the imprint area to each of an inspection position by means of the inspection unit, an application position by means of the dispenser, and a contacting position by means of the holding unit. Also, the controller causes the inspection unit to perform inspection of the imprint area in association with the movement of the imprint area by means of the movable unit.

Abstract: Methods are presented for facilitating fabrication of nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate; providing first material layers and second material layers above the substrate, the first material layers interleaved with the second material layers; removing portions of the first material layers and second material layers, the removing forming a plurality of nanowire stacks, including first material nanowires and second material nanowires; removing the first material nanowires from at least one nanowire stack; and removing the second material nanowires from at least one other nanowire stack, where the at least one nanowire stack and at least one other nanowire stack include a p-type nanowire stack(s) and a n-type nanowire stack(s), respectively.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: An object of the present invention is to provide a method which enable a material to be fully embedded into a recess portion with a deposition film left in the recess portion. A method in one embodiment comprises: a first irradiation step of irradiating a deposition film formed on an opening portion of a recess portion in a substrate with a particle beam in a direction at a first angle with respect to a substrate in-plane direction, to remove part of the deposition film in a thickness direction; and a second irradiation step of, after the first irradiation step, irradiating the deposition film with the particle beam in a direction at a second angle which is closer to perpendicular to the substrate in-plane direction than the first angle is, to remove part of the remaining deposition film in the thickness direction.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: A method of depositing a layer includes spraying a source gas and a reactant gas onto a substrate disposed on a susceptor unit using at least one source gas spray nozzle and at least one reactant gas nozzle to form a first source gas region and a first reactant gas region on the substrate, respectively, moving the susceptor unit by a distance corresponding to a width of the source gas spray nozzle or a width of the reactant gas spray nozzle in a first direction, and spraying the source gas and the reactant gas onto the first reactant gas region and the first source gas region using the source gas spray nozzle and the reactant gas nozzle, respectively, to form a first monolayer.

Abstract: An oxide semiconductor layer is formed, a gate insulating layer is formed over the oxide semiconductor layer, a gate electrode layer is formed to overlap with the oxide semiconductor layer with the gate insulating layer interposed therebetween, a first insulating layer is formed to cover the gate insulating layer and the gate electrode layer, an impurity element is introduced through the insulating layer to form a pair of impurity regions in the oxide semiconductor layer, a second insulating layer is formed over the first insulating layer, the first insulating layer and the second insulating layer are anisotropically etched to form a sidewall insulating layer in contact with a side surface of the gate electrode layer, and a source electrode layer and a drain electrode layer in contact with the pair of impurity regions are formed.

Abstract: An etching method containing, at the time of processing a substrate having a first layer containing titanium nitride (TiN) and a second layer containing a transition metal, selecting a substrate in which a surface oxygen content of the first layer is from 0.1 to 10% by mole, and applying an etching liquid containing a hydrofluoric acid compound and an oxidizing agent to the substrate and thereby removing the first layer.

Abstract: The present invention provides a method for selectively removing silicon carbide from the surface of a substrate in preference to silicon dioxide. The method comprises abrading a surface of substrate with a polishing composition that comprises a particulate abrasive, at least one acidic buffering agent, and an aqueous carrier.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: Provided is a method of manufacturing an organic light-emitting device including a graphene layer. The method of manufacturing an organic light-emitting device according to the present invention may include providing a graphene donor unit including a patterned graphene layer, providing a device unit, and attaching the graphene layer of the graphene donor unit to an organic part. The device unit may include a substrate, a lower electrode, and the organic part which are sequentially stacked, and the organic part may include a dopant. The graphene donor unit may include the graphene layer, a release layer, and an elastic stamp layer which are sequentially stacked.

Abstract: A Raman probe is used to detect crystal structure of a substrate undergoing thermal processing in a thermal processing system. The Raman probe may be coupled to a targeting system of a laser thermal processing system. The Raman probe includes a laser positioned to direct probe radiation through the targeting system to the substrate, a receiver attuned to Raman radiation emitted by the substrate, and a filter that blocks laser radiation reflected by the substrate. The Raman probe may include more than one laser, more than one receiver, and more than one filter. The Raman probe may provide more than one wavelength of incident radiation to probe the substrate at different depths.

Abstract: A method for producing self-aligned vias (SAV) is provided. Embodiments include forming a ILOS layer over a dielectric layer; forming pairs of spacers over the ILOS layer, each pair of spacers having a first filler formed between adjacent spacers, and a second filler formed between each pair of spacers; forming and patterning a first OPL to expose one second filler, spacers on opposite sides of the one second filler, and a portion of the first filler adjacent each of the exposed spacers; removing the one second filler to form a SAV, and SAV etching into the ILOS layer; forming a second OPL over the first OPL and in the SAV to form a SAV plug; removing OPL layers and etching into the ILOS layer down to the dielectric layer; forming a third OPL layer in spaces between the TEOS layer; and removing the SAV plug.

Abstract: High performance, high bandgap, lattice-mismatched, photovoltaic cells (10), both transparent and non-transparent to sub-bandgap light, are provided as devices for use alone or in combination with other cells in split spectrum apparatus or other applications.

Abstract: Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.

Abstract: An image forming apparatus includes image carriers; an exposing unit that forms latent images on the image carriers; a developing unit that develops the latent images with toners of different colors from each other; a first transfer unit that forms a color image by superimposing and transferring the developed images onto a second image carrier; a test pattern forming unit that forms, on the image carriers, test patterns to be transferred onto the second image carrier; and test pattern detection units capable of detecting the test patterns transferred onto the second image carrier in different positions from each other in a main-scanning direction. The test pattern forming unit selectively switches, depending on a width of the test patterns in the main-scanning direction, whether to form each of the test patterns in a position detectable by the corresponding one of the test pattern detection units.