Abstract: A plasma processing method includes etching a removing target film by supplying onto a peripheral portion of a substrate being rotated a first processing liquid containing hydrofluoric acid and nitric acid at a first mixing ratio; and etching the removing target film by, after supplying the first processing liquid onto the substrate, supplying onto the peripheral portion of the substrate being rotated a second processing liquid containing the hydrofluoric acid and the nitric acid at a second mixing ratio in which a content ratio of the hydrofluoric acid is lower and a content ratio of the nitric acid is higher than in the first processing liquid. When removing the removing target film made of SiGe, amorphous silicon or polysilicon from the peripheral portion thereof, an underlying film, for example, a film made of SiO2, which exists under the removing target film, can be appropriately left.

Abstract: Methods of forming the same include forming a stack of layers of alternating materials, including first layers of sacrificial material and second layers of channel material. The first layers are recessed relative to the second layers with an etch that etches the second layers at a slower rate than the first layers to taper ends of the second layers. First spacers are formed in recesses formed by recessing the first layers. Second spacers are formed in recesses formed by recessing the first layers. The first spacers are etched to expose sidewalls of the second spacer. Source/drain extensions are formed in contact with exposed ends of the second layers.

Abstract: According to one embodiment, a substrate processing method includes providing a substrate containing Si raised features, depositing a conformal film on the Si raised features, and performing a spacer etch process that removes horizontal portions of the conformal film while substantially leaving vertical portions of the conformal film to form sidewall spacers on the Si raised features, the performing including a) exposing the substrate to a plasma-excited first process gas consisting of H2 gas and optionally an inert gas, and b) exposing the substrate to a plasma-excited second process gas containing i) NF3, O2, H2, and Ar, ii) NF3, O2, and H2, iii) NF3 and O2, iv) NF3, O2, and Ar, v) NF3 and H2, or vi) NF3, H2, and Ar. The method further includes removing the Si raised features while maintaining the sidewall spacers on the substrate. The removing may be performed using steps a) and b).

Abstract: Organic coating compositions, particularly antireflective coating compositions, are provided that comprise that comprise a component that comprises one or more uracil moieties. Preferred compositions of the invention are useful to reduce reflection of exposing radiation from a substrate back into an overcoated photoresist layer and/or function as a planarizing, conformal or via-fill layer.

Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin.

Abstract: Processing methods comprising depositing a film on a substrate surface and in a surface feature with chemical planarization to remove the film from the substrate surface, leaving the film in the feature. A pillar is grown from the film so that the pillar grows orthogonally to the substrate surface.

Abstract: In a method for processing a target object including a conductive layer and an insulating film formed on the conductive layer, the insulating film is etched by plasma treatment of a fluorine-containing gas to form an opening in the insulating film. A barrier film is formed to cover a surface of the insulating film and a surface of the conductive layer which is exposed through the opening formed in the insulating film. The target object having the barrier film is placed in an atmospheric environment, and the barrier film is removed from the target object by isotropically etching the barrier film. The target object is maintained in a depressurized environment from start of etching the insulating film to end of forming the barrier film. The barrier film is conformally formed on the surfaces of the insulating film and the conductive layer exposed through the opening formed in the insulating film.

Abstract: The method comprises contacting a silicon substrate with a silver salt and an acid for a time effective to produce spikes having a first end disposed on the silicon substrate and a second end extending away from the silicon substrate. The spikes have a second end diameter of about 10 nm to about 200 nm, a height of about 100 nm to 10 micrometers, and a density of about 10 to 100 per square microns. The nanostructures provide antimicrobial properties and can be transferred to the surface of various materials such as polymers.

Abstract: The present invention relates to a CMP slurry composition, for an organic film, for polishing an organic film and an organic film polishing method using same, the CMP slurry composition comprising: a polar solvent and/or a non-polar solvent; metal oxide abrasives; an oxidant; and a heterocyclic compound, wherein the heterocyclic compound, as a heteroatom, comprises one or two of oxygen (O) atom, sulfur (S) atom and nitrogen (N) atom and has carbon content of 50-95 atom %.

Abstract: The present invention provides an etching liquid composition consisting of an aqueous solution that contains (A) 0.1 to 30 mass % of at least one type of oxidizing agent selected from among ferric ions and cupric ions; (B) 0.1 to 20 mass % of hydrogen chloride, and an etching method using it.

Abstract: The dicing method comprises the steps of providing a substrate (1) of semiconductor material, the substrate having a main surface (10), where integrated components (3) of chips (13) are arranged, and a rear surface (11) opposite the main surface, fastening a first handling wafer above the main surface, thinning the substrate at the rear surface, and forming trenches (20) penetrating the substrate and separating the chips by a single etching step after the substrate has been thinned.

Abstract: A method for producing patterns in a layer to be etched, from a stack including at least the layer to be etched and a masking layer overlying the layer to be etched, with the masking layer having at least one pattern. The method includes modifying a first area of the layer to be etched by ion implantation through the masking layer; depositing a buffer layer to cover the pattern of the masking layer; modifying another area of the layer to be etched, different from the first area, by ion implantation through the buffer layer, to a depth of the layer to be etched greater than the implantation depth of the preceding step of modifying; removing the buffer layer; removing the masking layer; removing the modified areas by etching them selectively to the non-modified areas of the layer to be etched.

Abstract: An element substrate is formed as a lens array substrate on which a plurality of lenses are formed. In a method of manufacturing the lens array substrate, first recess sections are formed on one surface of the substrate, and then a plurality of lens surfaces, which include concave surfaces, are formed at the bottoms of the first recess sections 195. Subsequently, after a light-transmitting lens layer is formed to fill the inside of the first recess sections, flattening is performed while the lens layer is removed. Here, the surface of the lens layer on a side opposite to the substrate is a planar surface which is contiguous to an outside area that is positioned on the outer side of the first recess sections on the one surface of the substrate.

Abstract: An array structure and a manufacturing method thereof are disclosed. The method for manufacturing the array structure includes: forming a gate insulating layer on a glass substrate; and etching the gate insulating layer at a position corresponding to a source/drain signal access terminal, and forming a through-hole structure provided with an outward-inclined side wall in the gate insulating layer. Conductive films in the source/drain signal access terminal and a gate signal access terminal which have wires thereof alternate with each other have a same height, so that the forces applied to conductive balls can be more uniform, and hence the conductivity can be improved.

Abstract: A material modification assembly comprises an energy source for generating light beams to modify a substrate. A computing device generates pattern script(s) based on at least one parameter of the modification. The computing device also generates process script(s) including a type of pulse scripts to be used with the light beams and are based on at least one parameter of the interaction between the energy source and the substrate. The computing device combines the pattern script(s) with the process script(s) and generates command signals based on the combination. The computing device transmits the command signals to one or more additional devices of the material modification assembly to facilitate modifying the light beams for the modification to the substrate such that the modification includes a pattern on at least a surface of the substrate having dimensions and includes two or more discrete material alterations or changes spatially overlapped within the pattern.

Abstract: Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. According to one embodiment, a substrate processing method includes providing a substrate containing raised contacts in a first dielectric film and a second dielectric film above the first dielectric film, depositing a metal-containing film on the second dielectric film, and forming a patterned metal-containing film by etching mask openings in the metal-containing film. The method further includes anisotropically etching recessed features in the second dielectric film above the raised contacts using the patterned metal-containing film as a mask, where the anisotropically etching forms a metal-containing sidewall protection film by redeposition of a portion of the patterned metal-containing film on sidewalls of the recessed features.

Abstract: Provided is a method of manufacturing a thin film transistor satisfying the relation of L<5 ?m. The method includes a process of forming a streak portion by performing transfer printing on a support using a release member which is provided with an ink streak portion for forming source and drain electrodes and has mold releasability, and baking the streak portion to thereby form the source electrode constituted by a conductor and the drain electrode constituted by a conductor. In the method manufacturing a thin film transistor in which the source and drain electrodes obtained above, a semiconductor layer, an insulator layer, and a gate electrode constituted by a conductor are laminated, after the baking, in a laminated cross section of the thin film transistor to be manufactured is set to A and a channel length thereof is set to L, the ink streak portion is provided so as to satisfy the condition of L/A?0.05.

Abstract: An example of a method of forming a printhead includes forming first and second resistors over a first dielectric, forming a first portion of a second dielectric over the first and second resistors and a second portion of the second dielectric over an exposed inclined surface of the first dielectric in a region between the first and second resistors, forming a metal conductor over the first and second portions of the second dielectric, and removing an inclined segment of the metal conductor from an inclined surface of the second portion of the second dielectric to expose the inclined surface of the second portion of the second dielectric.

Abstract: Disclosed is a substrate cleaning method. In this substrate cleaning method, a step (step 10) is performed wherein a removal target film and located above a processing target film is patterned; after step 10, a step (step 11) is performed wherein the patterned removal target film is used as an etching mask to perform anisotropic etching on the processing target film; after step 11, a step (step 12) is performed wherein the remaining removal target film on the processing target film is subjected to gas chemical etching; and after step 12, a step (step 14) is performed wherein a target substrate, which includes the surface of the processing target film, is irradiated with gas clusters, thereby cleaning the surface of the processing target film by removing non-reactive or non-volatile residues remaining on the surface of the processing target film.

Abstract: A lithography method comprises: providing a substrate with a target region; determining a topology of the substrate within the target region; determining a correcting telecentricity profile based on the topology of the substrate within the target region; providing a radiation beam; and projecting the radiation beam onto the target region of the substrate so as to form an image on the substrate. The radiation beam is such that a net direction of the total radiation received by one or more points in the target region of the substrate is chosen in dependence on the determined correcting telecentricity. The correcting telecentricity profile is such that the net direction of the total radiation received by at least one point in the target region of the substrate is chosen so as to at least partially correct for an overlay error introduced by a curvature of a surface of the substrate at said point.

Abstract: A probe pin includes a coil spring, a first plunger, a first end of which is inserted from a first end of the coil spring into the coil spring and a second end of which is exposed to outside of the coil spring, and a second plunger, a first end of which is inserted from a second end of the coil spring into the coil spring to be in contact with the first end of the first plunger and a second end of which is exposed to the outside of the coil spring. The second plunger includes at least one elastic arm extending from the second end of the second plunger, and a touch portion is provided at a leading end of the elastic arm and displaceable in a direction intersecting an axial center direction when pressing force in the axial center direction is applied to the touch portion.

Abstract: A substrate processing system includes a processing chamber. A pedestal and a showerhead are arranged in the processing chamber. A surface plasmon resonance (SPR) fiber has a central portion disposed in the processing chamber, and opposing ends disposed outside the processing chamber. A light source provides input light at one end of the SPR fiber, and a detector receives output light from the other end of the SPR fiber. Surface plasmon waves and evanescent waves constitute the output light, which is processed and analyzed to determine a condition of the processing chamber.

Abstract: According to one example, a method includes epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor structures running perpendicular to the substrate. The method further includes forming a gate layer on the substrate, the gate layer contacting the elongated semiconductor structures. The method further includes performing a planarization process on the gate layer and the elongated semiconductor structures, and epitaxially growing second portions of the plurality of elongated semiconductor structures, the second portions comprising a different material than the first portions.

Abstract: A method of manufacturing a semiconductor device includes alternately stacking mold insulating layers and sacrificial layers on a substrate; forming channel holes penetrating through the mold insulating layers and the sacrificial layers and allowing recessed regions to be formed in the substrate; cleaning a surface of the recessed regions in such a manner that processes of forming a first protective layer in an upper region of the channel holes and performing an anisotropic dry etching process on the recessed regions in a lower portion of the channel holes are alternately repeated one or more times, in-situ; and forming epitaxial layers on the recessed regions of the substrate.

Abstract: Methods include exposing polysilicon to an aqueous composition comprising nitric acid, poly-carboxylic acid and ammonium fluoride, and removing a portion of the polysilicon selective to an oxide using the aqueous composition.

Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.

Abstract: Methods and systems for selective silicon anti-reflective coating (SiARC) removal are described. An embodiment of a method includes providing a substrate in a process chamber, the substrate comprising: a resist layer, a SiARC layer, a pattern transfer layer, and an underlying layer. Such a method may also include performing a pattern transfer process configured to remove the resist layer and create a structure on the substrate, the structure comprising portions of the SiARC layer and the pattern transfer layer. The method may additionally include performing a modification process on the SiARC layer of the structure, the modification converting the SiARC layer into a porous SiARC layer. Further, the method may include performing a removal process of the porous SiARC layer of the structure, wherein the modification and removal processes of the SiARC layer are configured to meet target integration objectives.

Abstract: A method for embossing at least one microstructure or nanostructure with an embossing die that has at least one embossing structure with the following steps, in particular the following sequence: aligning the embossing structure of the embossing die relative to a metering device, metering an embossing material in the embossing structure by means of the metering device, at least partial hardening of the embossing material and embossing of the embossing material, characterized in that the embossing structures point in a gravitational direction (G) at least in the case of the metering. In addition, the invention relates to a corresponding device.

Abstract: This disclosure provides an epitaxial wafer, which includes: a silicon wafer having a central area and an extremity area enclosing the central area, the extremity area having a stepped profile; and an nitride epitaxial layer formed on the silicon wafer; wherein, the stepped profile has a width between 10 and 1500 ?m and a height between 1 and 500 ?m.

Abstract: Implementations of the methods and apparatus disclosed herein relate to pore sealing of porous dielectric films using flowable dielectric material. The methods involve exposing a substrate having an exposed porous dielectric film thereon to a vapor phase dielectric precursor under conditions such that a flowable dielectric material selectively deposits in the pores of the porous dielectric material. The pores can be filled with the deposited flowable dielectric material without depositing a continuous film on any exposed metal surface.

Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.

Abstract: Methods for selectively depositing a cobalt layer are provided herein. In some embodiments, methods for selectively depositing a cobalt layer include: exposing a substrate to a first process gas to passivate an exposed dielectric surface, wherein the substrate comprises a dielectric layer having an exposed dielectric surface and a metal layer having an exposed metal surface; and selectively depositing a cobalt layer atop the exposed metal surface using a thermal deposition process.

Abstract: Described are materials and methods for processing (polishing or planarizing) a substrate that contains pattern dielectric material using a polishing composition (aka “slurry”) and an abrasive pad, e.g., CMP processing.

Abstract: Chemical Mechanical Planarization (CMP) polishing compositions comprising composite particles, such as ceria coated silica particles, offer tunable polishing removal selectivity values between different films. Compositions enable high removal rates on interconnect metal and the silicon oxide dielectric while providing a polish stop on low-K dielectrics, a-Si and tungsten films. Chemical Mechanical Planarization (CMP) polishing compositions have shown excellent performance using soft polishing pad.

Abstract: A substrate with a lithium imide layer, a LED with a lithium imide layer and a manufacturing method of the LED are provided. The substrate includes a lithium niobate layer and a lithium imide layer. The lithium imide layer is formed on a surface of the lithium niobate layer.

Abstract: Provided are a method for preparing a thin film or a thick film, including: a first step of providing a porous substrate capable of supplying silicon; a second step of applying zeolite seed crystals onto the surface of the porous substrate; a third step of coating the seed crystals-applied porous substrate with an aqueous solution containing a structure-directing agent; and a fourth step of forming and growing a film from the seed crystals by the secondary growth above a temperature at which moisture inside the seed crystals-applied porous substrate prepared in the third step can form steam, and a film prepared by the method. The film manufacturing method of the present invention is a simple manufacturing process, and thus has high reproducibility and high throughput. Since a synthetic gel is not used and a solution is used, the unnecessary consumption of materials, environmental pollution, and waste of a synthetic gel can be prevented while not necessitating drying and washing of a film.

Abstract: A system for heating substrates while being transported between processing chambers is disclosed. The system comprises an array of light emitting diodes (LEDs) disposed in the transfer chamber. The LEDs may be GaN LEDs, which emit light at a wavelength which is readily absorbed by silicon, thus efficiently and quickly heating the substrate. A controller is in communication with the LEDs. The LEDs may be independently controllable, so that the LEDs that are disposed above the substrate as it is moved from one processing chamber to another are illuminated. In other words, the illumination of the LEDs and the movements of the substrate handling robot may be synchronized by the controller.

Abstract: A method for manufacturing a semiconductor device in accordance with the present invention includes the steps of preparing a semiconductor substrate, placing the semiconductor substrate on an electrostatic chuck, chucking the semiconductor substrate after raising a temperature of the electrostatic chuck to a first temperature, raising a temperature of the electrostatic chuck to a second temperature which is higher than the above-described first temperature in a state where the semiconductor substrate is chucked, and performing a treatment to the semiconductor substrate in a state where a temperature of the electrostatic chuck is maintained at the above-described second temperature.

Abstract: Optical waveguiding part (300), which waveguiding part is arranged to convey light through an output facet (30) of the waveguiding part, which waveguiding part comprises a ridge waveguide comprising a semiconductor substrate (320) and a semiconductor light-conveying ridge, wherein the output facet is set at an angle (?) in relation to a main direction (z) of light along the said waveguide, so that light travelling in the waveguide along said main direction has an angle of incidence towards the facet of between 2° and 14° and is reflected towards a first side (301) of the said ridge, wherein the waveguide comprises an MMI (Multi Mode Interferometer) (310), arranged to create an output image substantially at the output facet.

Abstract: A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor.

Abstract: A method of preparing a display device including a plurality of pixels where a plurality of gate lines cross a plurality of data lines, respectively, each of the pixels including a thin film transistor (TFT) region and a display region, the method can include: forming a thin film transistor (TFT) in the TFT region; and forming a light emitting element for displaying images based on signals from the TFT in the display region, in which a metallic layer is disposed in the TFT region for electrical connection of the TFT; and a light absorbing layer configured to absorb at least part of light propagating toward the metallic layer is disposed on the metallic layer between the metallic layer and one of a gate insulating layer, an active layer, an interlayer dielectric layer and a substrate.

Abstract: A plasma processing apparatus includes a processing chamber, a carrier wave group generation unit and a plasma generation unit. The carrier wave group generation unit is configured to generate a carrier wave group including a plurality of carrier waves having different frequencies in a frequency domain. The carrier wave group is represented by an amplitude waveform in which a first peak and a second peak of which absolute value is smaller than an absolute value of the first peak alternately appear in a time domain. The plasma generation unit is configured to generate a plasma in the processing chamber by using the carrier wave group.

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove an exposed silicon oxide portion faster than an exposed silicon nitride portion. The inclusion of the oxygen-containing precursor may suppress the silicon nitride etch rate and result in unprecedented silicon oxide etch selectivity.

Abstract: A method of forming fine patterns of semiconductor devices is disclosed. The method comprises forming a hard mask layer on an etch target, which includes first and second regions. The hard mask layer may further have first and second preliminary mask patterns formed on the same. Furthermore, a spacer layer may be formed on the first and second preliminary mask patterns. The spacer layer and the first and second preliminary mask patterns may be partially removed to form first and second spacers on sidewalls of the first and second preliminary mask patterns, respectively. The second spacer in the second region may have a top surface higher than a top surface of the first spacer in the first region. The height differences between the spacers allow forming of first and second patterns in the first and second regions, and thereby forming fine patterns of semiconductor devices.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: The present invention provides a method for fabricating an oriented zeolite film including preparing a metal substrate and zeolite crystal with an aspect ratio of at least 2; laying the zeolite crystal on the metal substrate to obtain a first metal substrate; applying a precursor solution containing a first structure directing agent and a solvent on the first metal substrate to obtain a second metal substrate; placing the second metal substrate in a sealed container containing a predetermined amount of the solvent; and heating the sealed container at 100-550° C. for at least 15 minutes. Thus, a continuous oriented zeolite film is formed with uniform thickness and improved anti-corrosion ability.

Abstract: The present invention discloses a method for electroless plating of a metal or metal alloy onto a metal or a metal alloy structure comprising a metal such as molybdenum or titanium and alloys containing such metals. The method comprises the steps of activation, treatment in an aqueous solution comprising at least one nitrogen-containing compound or a hydroxy carboxylic acid and electroless plating of a metal or metal alloy.

Abstract: A first etching rate of the first conductive film is calculated by acquiring correlation between an opening ratio of an etching mask and an etching rate of an etching target film, and then, performing a first dry etching to a first conductive film formed on a first wafer. Next, a second etching mask is formed on a second conductive film formed on a second wafer, and an etching time of the second conductive film is determined from the correlation between the opening ratio and the etching rate, the first etching rate, and a film thickness of the second conductive film when the second conductive film is subjected to a second dry etching in time-controlled etching.

Abstract: A semiconductor layer sequence includes a first nitridic compound semiconductor layer, a second nitridic compound semiconductor layer, and an intermediate layer arranged between the first and second nitridic compound semiconductor layers. Beginning with the first nitridic compound semiconductor layer, the intermediate layer and the second nitridic compound semiconductor layer are arranged one after the other in a direction of growth of the semiconductor layer sequence and are adjacent to each other in direct succession. The intermediate layer has a lattice constant different from the lattice constant of the first nitridic compound semiconductor layer at least at some points. The second nitridic compound semiconductor layer is lattice-adapted to the intermediate layer at least at some points.

Abstract: Etch masks and methods of dicing semiconductor wafers are described. In an example, an etch mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. The etch mask also includes a plurality of particles dispersed throughout the water-soluble matrix. The plurality of particles has an average diameter approximately in the range of 5-100 nanometers. A ratio of weight % of the solid component to weight % of the plurality of particles is approximately in the range of 1:0.1-1:4.