Abstract: Generating a universal graphical desktop sharing protocol is disclosed. The universal graphical desktop sharing protocol is configured to communicate information (e.g., a sequence of one or more desktop sharing events) that has been translated from a first graphical desktop sharing protocol and is available to be translated into a final graphical desktop sharing protocol.

Abstract: An apparatus and system for processing I/O from a data storage chassis, the apparatus and system comprising a first I/O printed circuit board (PCB) including I/O wafers; wherein the I/O wafers of the first I/O PCB are enabled to receive I/O from the data storage chassis; a second I/O PCB including I/O wafers; wherein the I/O wafers of the second I/O PCB are enabled to receive I/O from the data storage chassis; wherein the I/O wafers of the first I/O PCB is constructed and configured to receive the I/O wafers of the second I/O PCB.

Abstract: A PWM circuit is disclosed in the application, which includes: a PWM counter, a reference value setting register, a frequency multiplier and a comparator, where the frequency multiplier is adapted to increase the frequency of a clock signal input and to output the clock signal with the increased frequency to the PWM counter. An LED drive circuit is further disclosed in the application. The frequency of a PWM input clock signal is increased to N times of the original frequency of the PWM input clock signal by the frequency multiplier, so that the counting cycle of the PWM counter is shortened to 1/N of the original counting cycle of the PWM counter. Therefore, in the dynamic LED display screen, the refresh frequency can be increased to N times of the original refresh frequency while the original resolution is maintained.

Abstract: A clock generating circuit includes oscillators each having a delay rise vote input, a delay fall vote input, a delay rise output, a delay fall output, and a clock output; a vote rise circuit having inputs coupled individually to the delay rise outputs of the oscillators, and an output coupled in common to the delay rise vote inputs of the oscillators; a vote fall circuit having inputs coupled individually to the delay fall outputs of the oscillators, and an output coupled in common to the delay fall vote inputs of the oscillators; and a vote clock circuit having inputs coupled individually to the clock outputs of the oscillators, and an output for providing a synchronized clock signal.

Abstract: A display apparatus displaying video input through various ports is provided. The display apparatus includes a board which is disposed behind a display module, wherein the board includes a universal serial bus (USB) port which receives a USB standard signal, a decoder which decodes a video signal from the USB standard signal and outputs a decoded signal, a video output unit which outputs a displayable video signal to the display module corresponding to the video signal, wherein the USB port is disposed at an edge of a first side of the board, and the video output unit is disposed at an edge of a second side of the board which is different from the first side of the board.

Abstract: An interface device is for coupling a payment card to an electronic device so as to allow the electronic device to access the payment card. The interface device includes a housing, a switching unit movably connected to the housing, a circuit board brought to move relative to the housing by the switching unit, a card interface disposed on the circuit board, and a connecting interface to be coupled to the electronic device. The connecting interface and the circuit board cooperate to define a card slot for containing the payment card therein. The interface device is operable to switch between a retracted state, in which the connecting interface is contained in the housing, and an exposed state, in which the connecting interface protrudes from the housing.

Abstract: A controller-bridge architecture in which a bridge device coupled with the non-volatile memory (NVM) handles inline read-modify-write function under instructions from a controller device is disclosed. In some embodiments, instead of transferring an entire range of data (e.g., a whole NVM page) across a bus between the bridge and the controller twice (once before and once after modification), only the modification data is sent by the controller to the bridge across the bus. The bridge in some embodiments also handles error correction and/or RAID parity striping in the read-modify-write process.

Abstract: This disclosure provides a network security architecture that permits installation of different software security products as virtual machines (VMs). By relying on a standardized data format and communication structure, a general architecture can be created and used to dynamically build and reconfigure interaction between both similar and dissimilar security products. Use of an integration scheme having defined message types and specified query response framework provides for real-time response and easy adaptation for cross-vendor communication. Examples are provided where an intrusion detection system (IDS) can be used to detect network threats based on distributed threat analytics, passing detected threats to other security products (e.g., products with different capabilities from different vendors) to trigger automatic, dynamically configured communication and reaction.

Abstract: A data storage device to communicate with a host is disclosed. The data storage device includes a controller to select a SATA mode or a USB mode and a SATA connector coupled to the controller. If the USB mode is selected for communication with the host, a plurality of pins of the SATA connector are utilized to transmit USB signals from the controller to the host.

Abstract: In some embodiments a detector detects a host or device coupled via a link. A port negotiates with a port of the detected host or device and determines whether to operate as a host and/or as a device. Other embodiments are described and claimed.

Abstract: An optical-electrical conversion module includes a circuit board, a planar optical waveguide formed on the circuit board, two first lenses and two second lenses mounted above the planar optical waveguide, a base plate electrically connected to the circuit board, and an optical signal emitting member and an optical signal receiving member mounted on the base plate. The planar optical waveguide forms two inclined surfaces. The base plate is positioned above the second lenses. Optical signals are reflected by the inclined surface, and are transmitted to the optical signal receiving member. The optical signal receiving member converts the optical signals to electrical signals to transmit to the circuit board. Electrical signals of the circuit board are converted to optical signals via the optical signal emitting member, and then are transmitted to the planar optical waveguide. The present disclosure further provides an optical transmission connecting assembly using the optical-electrical conversion module.

Abstract: In a switching node, high-speed and advanced service protocol processing function is achieved by utilizing an external control server without affecting performance of conventional service protocol processing. Specifically, a forwarding engine has PCI express and an LAN interface. Depending on a type of an input packet, destination of the packet is switched to the PCI express side for conventional network service and to the LAN interface side for extended network service that cooperates with the external control server. A CPU having the PCI express and the LAN interface is provided ahead of the LAN interface. The CPU performs communication of service inquiry with the external control server at high speed via the LAN interface. After response from the control server is obtained, setting of the forwarding engine is performed through the PCI express.

Abstract: An information processing apparatus including processing units and a connection control unit that controls the connections between the processing units, in which the connection control unit is provided with a table creation unit which, with respect to a first logical channel established with a processing unit, creates table information showing a correspondence between logical channels without designating a logical channel that corresponds to the first logical channel when there is no second logical channel established with another processing unit that corresponds to the first logical channel, a table storage unit that stores the table information created by the table creation unit, and a table update unit that updates the table information for the second logical channel that is stored in the table storage unit so as to configure the first logical channel as a logical channel that corresponds to the second logical channel when there is a second logical channel.

Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

Abstract: An information processing device creates a management table of bridge addresses by allocating the bridge addresses to a plurality of bridges, respectively, and, when detecting one access to one device of a plurality of devices, refers to the management table, performs, based on the management table referred to, cancelling allocation of a bridge address of the bridge addresses and reallocating the bridge address to one or more of the plurality of bridges to enable execution of the one access, and updates the management table in regard to the bridge address cancelled and reallocated. Consequently, the information processing device can simultaneously use bridges the number of which exceeds a predetermined number even when the bridges the number of which exceeds the predetermined number are provided in the information processing device and therefore bridge addresses run out.

Abstract: Multi-channel universal serial bus (USB) to subrate channel methods are disclosed. According to an aspect, a method includes providing a system comprising a USB interface and a multi-channel interface configured to communicatively connect to a plurality of subrate channels. The method also includes communicatively connecting the subrate channels with a computing device via the USB interface. Further, the method includes communicating, to the computing device, connection specifications for the subrate channels.

Abstract: A system-on-chip bus system and an operating method of the same are provided. The bus system includes a master device, a slave device and an interconnector coupled between the master device and the slave device. The interconnector includes a synchronization/compaction block to control traffic provided from a master device to a slave device. When a write request traffic and a corresponding write data traffic are all provided from the master device, the synchronization/compaction block may transfer the two traffics to the slave device.

Abstract: A bus system includes a plurality of master devices each of which issues a transaction request having a first transaction identifier with a first bit width and a slave device responding to the transaction request having a second transaction identifier with a second bit width and supplying a transaction response having the second transaction identifier to the plurality of master devices. The embodiment further comprises a bus configured to connect one of the plurality of master devices and the slave device; and an ID converter configured to connect the bus and the slave device and to map the first transaction identifier to the second transaction identifier for providing the second transaction identifier to the slave device and map the second transaction identifier to the first transaction identifier for providing the first transaction identifier to the one of the plurality of master devices.

Abstract: A common interface (CI)/conditional access (CA) module is used to transmit a conditional access data/command and a transport stream in an interleaving manner between a common interface card and an integrated circuit module having a conditional access module. With the aid of the CI/CA module, a same port can be shared for transmitting the conditional access data/command and the transport stream, instead of using two different and separated ports.

Abstract: A connector apparatus and the associated method are provided for bridging data between entities, such as between data source(s) and data target(s). In a method, first and second data bridge connections are established between a connector apparatus and a data source and between a connector apparatus and a data target, respectively. Each data bridge connection includes a data pipe having one or more data flows with each data flow dedicated to a particular data type. The method includes sending a polling request from the connector apparatus to the data source via the first data bridge connection and receiving data from the data source over the first data pipe in response to the polling request. The method includes sending the received data to the data target over the second data pipe when the data target has subscribed to the data received from the data source over the first data pipe.

Abstract: A method is provided. A communication is received by an input pin of an IC over a single-wire bus, where the communication includes a command byte. If the command byte is an initialization command byte, a self-addressing operation is performed to identify a bus address for the IC. Alternatively, if the command byte is a data movement command byte, a data movement operation is performed. When data movement operation is performed, the bus interface of the IC is set from the transparent mode to the operational mode if an operation address from the command byte matches the bus address so that a register identified in the command byte can be accessed and data movement with the register can be performed.

Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

Abstract: In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.

Abstract: A data storage system and associated method of using may generally have at least a data storage device that has independent first and second interfaces respectively connecting the data storage device to a host controller and an auxiliary controller. The auxiliary controller can be configured to provide system information to the data storage device prior to a synchronized connection being established between the data storage device and the host controller.

Abstract: A communication interface hub includes multiple ports, where one of the ports is an upstream port operative to be in direct and/or indirect communication with a host and at least one other of the ports is a downstream port operative to be in direct and/or indirect communication with at least one device. At least one hub core is coupled to the ports and implements at least one physical hub, and at least one virtual hub core is coupled to the ports and implements at least one virtual hub. The virtual hub is detectable as at least one physical hub by the host to cause the host to allocate an additional time delay in waiting for responses to signals output by the host.

Abstract: A communication network for a low-voltage switchboard comprising three types of communication bus. The first communication bus is designed to provide a first communication channel with at least one electronic protection device. A second communication bus is designed to provide a second communication channel with said electronic protection device. At least one third communication bus (13) is designed to provide a third communication channel between said at least one protection and control unit and one or more additional electronic modules (6A, 6B, 6C, 6E, 6F). The second communication bus is associated with a second, higher user access level than the first user access level associated with said first communication bus.

Abstract: Multi-channel universal serial bus (USB) to subrate channel systems and methods are disclosed. According to an aspect, a system includes a USB interface configured to communicatively connect to a computing device. The system may also include a multi-channel interface configured to communicatively connect to multiple subrate channels. Further, the system may include a controller configured to communicatively connect the subrate channels with the computing device via the USB interface. The controller may also be configured to communicate, to the computing device, connection specifications for the subrate channels.

Abstract: An internal bus architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.

Abstract: A memory interface chip is disclosed and includes a data output unit and a control module, wherein the data output module receives data from an external source. The data output unit can be selectively connected to different memory structures. The data output unit includes a first output channel and a second output channel, wherein the channels respectively generate a first output signal and a second output signal based on the data received. The control module selectively closes off the first output channel or the second output channel based on the memory architecture of the memory connected to the data output unit.

Abstract: A field bus network adapter includes a first field bus connection configured to connect a first field bus cable, a second field bus connection configured to connect a second field bus cable, and N number of third field bus connections configured to connect a third cable each. The first field bus connection and the second field bus connection are connected to the N number of third field bus connections such that (i) data received at the first field bus connection are output at a first of the N number of third field bus connections, (ii) data received at an nth of the N number of third field bus connections are output at an (n+1)th of the N number of third field bus connections, and (iii) data received at an Nth of the N number of third field bus connections are output at the second field bus connection.

Abstract: In one embodiment, a method includes accessing a first field of a first link capabilities register of a first device having a protocol stack including a transaction layer and a link layer according to a first communication protocol and a physical layer of the protocol stack having a physical unit of a second communication protocol, using the first field as a pointer value to a location in a second link capabilities register of the first device, and using information from the location in the second link capabilities register to perform a configuration operation for a physical link coupled to the device. Other embodiments are described and claimed.

Abstract: Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field having a value. The request is then entered into one of a plurality of buffers having requests therein with the same identification field values. Which buffer receives the request may be based on a variety of techniques, such as random, least recently used, most full, prioritized, or sequential. Next, the buffered request is transmitted over a second bus. A response to the request is eventually received from the second bus, the response is transmitted over the first bus, and the request is then removed from the buffer. By entering the received request to the buffer with request with the same identification value, there is a reduced possibility of head-of-line request blocking when compared to a single buffer implementation.

Abstract: Embodiments include apparatuses, systems, and methods for reduced pin cross triggering to enhance a debug experience. A time-division packetizing (TDP) technique may be employed to facilitate communication of triggers between integrated circuits (ICs) connected in series forming a TDP communication ring. The ICs on the TDP communication ring may each include a cross trigger interconnect structure for interpreting between trigger signals and hardware core instructions. The serial TDP communication across the ICs on the TDP communication ring allows the ICs to be connected in a manner that each cross trigger interconnect structure on each IC may function as if it were part of a single cross trigger interconnect structure across all of the ICs on the TDP communication ring. The individual ICs may operate asynchronously and a trigger clock may be passed along with other trigger data to implement the debugging techniques uniformly on each IC.

Abstract: A method of transmission-reception over a serial bus placed, when idle, in a first state at a first voltage, including: a transmit circuit capable of coding a transmission according to a first protocol in which the respective states of the bits are conditioned by time periods of fixed levels, indifferently in the first state or in a second state at a second voltage smaller than the first one; a receive circuit capable of interpreting a communication according to the first protocol; and a protocol converter, interposed between the bus and the transmit and receive circuits, to convert the signals to be transmitted to a second protocol in which the respective states of the bits are conditioned by respective time periods of fixed levels in the first state, and to convert the received signals from the second protocol to the first protocol.

Abstract: A communication apparatus for carrying out communications to and from an external apparatus that includes a first interconnecting unit and a first non-transparent port and effects an interconnection for communications via the first non-transparent port is provided. The communication apparatus includes a second interconnecting unit that includes a second non-transparent port communicably connected to the first non-transparent port. The second interconnecting unit effects an interconnection for communications via the second non-transparent port. The second interconnecting unit performs, when the communication apparatus carries out communications to and from the external apparatus, address translation between an address for use by the communication apparatus and an address for use by the second non-transparent port.

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. In one example, the configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit. The rectangular islands of one row are oriented in staggered relation with respect to the rectangular islands of the next row. The left and right edges of islands in a row align with left and right edges of islands two rows down in the row structure. The data bus involves multiple meshes. In each mesh, the island has a centrally located crossbar switch and six radiating half links, and half links down to functional circuitry of the island. The staggered orientation of the islands, and the structure of the half links, allows half links of adjacent islands to align with one another.

Abstract: A disk array for a storage system that includes a dual controller disk array and a server includes a disk frame and two controller nodes. Each controller node includes a switch, where a port of the switch is connected to a port of a switch of a peer controller node. Each controller node is configured to detect whether the peer controller node is invalid through the port. When it has been detected that the peer controller node is invalid, a local controller node enables the peer controller node to send, through the port of the switch of the peer controller node, received data from the server to a port of a switch of the local controller node.

Abstract: An integrated data concentrator, so-called “sensor hub”, for a multi-sensor MEMS system, implements: a first interface module, for interfacing, in a normal operating mode, with a microprocessor through a first communication bus; and a second interface module, for interfacing, in the normal operating mode, with a plurality of sensors through a second communication bus; the sensor hub further implements a pass-through operating mode, distinct from the normal operating mode, in which it sets the microprocessor in direct communication with the sensors, through the first communication bus and the second communication bus. In particular, the sensor hub implements the direct pass-through operating mode in a totally digital manner.

Abstract: An apparatus and method for a Universal Serial Bus (USB) isolating device. An USB isolating device includes a downstream facing circuit and a upstream facing circuit. The downstream facing circuit is coupled to a peripheral device via a first pair of signals and is configured for detecting a speed at which the peripheral device is operating based on a first voltage configuration on the first pair of signals. The upstream facing circuit is coupled to the downstream facing circuit and a host/hub via a second pair of signals and is configured for communicating with the downstream facing circuit on the speed of the peripheral device and adaptively creating a second voltage configuration on the second pair of signals to facilitate the host/hub to adapt to the speed of the peripheral device.

Abstract: A source of video data may be coupled to a plurality of sinks using a wireless branch device with more than one connector. Numbers may be assigned to the connectors in a sequence depending on the wireless technology used by each connector. Examples of wireless technologies include DisplayPort, HDMI, and Wireless Gigabit Alliance. Sinks coupled to the branch device are interrogated to determine the number of connectors and each connector's wireless technology.

Abstract: An exemplary semiconductor circuit bus system includes: a first bus comprised of distributed buses and having a first transfer rate; a second bus with a second transfer rate higher than the first transfer rate; a transmission node; a bus interface (IF) to connect the transmission node to the first bus; a router which connects the first and second buses; and a reception node connected to the second bus. The bus IF controls the flow rate of data flowing through the transmission routes of the first bus by reference to information about the amounts of transmissible data of the transmission routes. The router allocates the amounts of transmissible data to the transmission routes of the first bus and provides information about the amounts of transmissible data of the transmission routes for the bus IF and also controls the flow rate of the data flowing through the second bus.

Abstract: An electrical circuit for driving a bus is described that includes at least one branch coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes a current detection unit coupled to the at least one branch, which is configured to detect a current through the at least one branch. The electrical circuit also includes an over-current determination unit coupled to both the current detection unit and the transmit data input. The over-current determination unit is configured to determine an over-current condition at the at least one branch based on the current at the at least one branch and the data at the transmit data input.

Abstract: Techniques are disclosed relating to coding data in an apparatus. In one embodiment, the apparatus includes a coder circuit coupled to a data bus, where the coder circuit is configured to receive an indication that data is being transmitted over the data bus from a first circuit to a second circuit. The coder circuit is configured to perform a coding operation on the data in response to receiving the indication. In some embodiments, the coder circuit is configured to operate in a mode in which the coder circuit captures data of a data transmission via the data bus without being specified as a participant of the data transmission. When the coder circuit is not operating in the mode, the coder circuit is not configured to capture data of a data transmission without being specified as a participant of the data transmission.

Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.

Abstract: An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.

Abstract: A processing system is disclosed. The processing system comprises a first integrated circuit. The first integrated circuit includes a processor core, a display interface and memory controller coupled to a first bus interface. The display interface is adapted to display graphical information generated by a graphics engine. A graphics engine is not on the first integrated circuit. The processing system includes a second bus interface for allowing communication with the first integrated circuit via the first bus interface. The second bus interface is adapted to allow for communication to a graphics engine.

Abstract: A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system.

Abstract: A bridging board configured for connecting a processor with a hard disk backboard includes a first signal connecting apparatus, a second signal connecting apparatus, a plurality of duplexer and a signal conditioner. The first signal connecting apparatus is electronically connected to the processor. The second signal connecting apparatus electronically connected to the hard disk backboard. Each duplexer has an input terminal electronically connected to the first signal connecting apparatus, and two output terminals electronically connected to the second signal connecting apparatus to allow the processor to communicate with the backboard via the bridging board. The signal conditioner is electronically connected between the first signal connecting apparatus and the second signal connecting apparatus to amplify signals transmitted from the processor to the hard disk backboard.

Abstract: Techniques for management of target devices are provided. User input for management of a target device may be received. The user input may be converted into a first format. The first format may be encapsulated into a second format and sent over a communications channel. The second format may be un-encapsulated to recover the first format. The first format may be provided to the target devices.

Abstract: An interface controller, coupling a device main body of an external electronic device to a host, is disclosed, which transmits a termination-on signal to the host prior to a mechanically stable state of a device main body of the external electronic device. When the device main body has not reached the mechanically stable state yet, the interface controller responds to the host with default link information in a delayed manner. The default link information is contained in the interface controller. When the device main body reaches the mechanically stable state, the interface controller transmits specific link information retrieved from the device main body to the host.