Abstract: A system, circuit and method for improving system-on-chip (SoC) bandwidth performance for high latency peripheral read accesses using a bridge circuit are disclosed. In one embodiment, the SoC includes the bridge circuit, one or more bus masters, at least one high bandwidth bus slave and at least one low bandwidth bus slave that are communicatively coupled via a high bandwidth bus and a low bandwidth bus. Further, the bus masters access the at least one low bandwidth bus slave by issuing an early read transaction request in advance to a scheduled read transaction request. Furthermore, the bridge circuit receives the early read transaction request and fetches data associated with the early read transaction request. In addition, the bridge circuit receives the scheduled read transaction request. The fetched data is then sent to the bus masters upon receiving the scheduled read transaction request.

Abstract: A bridge includes buses, a memory, a component module, an interface and an interrupt module. The component module transfers data between a host control module and a network device via the memory and the buses. The interface is connected between the memory and the network device and transmits status information to the memory via one of the buses. The status information indicates completion of a last data transfer between the network device and the host control module. An interrupt module, subsequent to the status information being transmitted to the memory, detects a first interrupt generated by the network device, and transmits an interrupt message to the component module via the memory and the one of the buses. The component module then generates a second interrupt detectable by the host control module. The second interrupt indicates completion of data transfer between the network device and the host control module.

Abstract: A data connector includes two different sets of wires that transport data between components of a computer system. A first set of wires transports data from a first component to a second component. A second set of wires transports data from the second component to the first component. The first set of wires is interlaced with the second set of wires so that each wire in the data connector transports data in the opposite direction of one or more neighboring wires.

Abstract: A method, system and computer program product are provided for implementing PCI-Express memory domains for single root virtualized devices. A PCI host bridge (PHB) includes a memory mapped IO (MMIO) domain descriptor (MDD) and an MMIO Domain Table (MDT) are used to associate MMIO domains with PCI memory VF BAR spaces. One MDD is provided for each unique VF BAR space size per bus segment connecting a single root IO virtualization (SRIOV) device to the PCI host bridge (PHB). The MDT used with the MDD includes having a number of entries limited to a predefined total number of SRIOV VFs to be configured. A VF BAR Stride, which may be further implemented as a VF BAR Stride Capability Structure, is provided to reduce the number of MDDs required to map SRIOV VF BAR spaces. A particular definition of the MDD is provided to reduce the number of MDDs required to at most one per SRIOV bus segment below a PHB.

Abstract: A data processing system includes a processor core, a system memory coupled to the processor core, an input/output adapter (IOA), and an input/output (I/O) host bridge coupled to the processor core and to the IOA. The I/O host bridge includes a register coupled to receive I/O messages from the processor core, a buffer coupled to receive I/O messages from the IOA, and logic coupled to the register and to the buffer that services I/O messages received from the register and from the buffer.

Abstract: An information handling system (IHS) remote input/output (I/O) connection system includes an enclosure having a power button, a communication bus connection point, and an audio connection point. A cable dongle extends from the enclosure. The cable dongle has a first end and a second end. The cable dongle also includes a connection from the power button on the enclosure on the first end to a communication connection point plug on the second end, which mates with a connection point plug on a remote I/O device card that enables a parallel (ACPI) S5-capable power button from the IHS to exist on the enclosure. The cable dongle further includes a communication cable coupled to the communication bus connection point on the first end and having a communication connection point plug on the second end. In addition, the cable dongle includes an audio cable coupled to the audio connection point on the first end and having an audio connection point plug on the second end.

Abstract: A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first terminal and a data terminal connected to the third terminal. In a case of performing communication by the first interface circuit, a fixed signal fixed at a predetermined level is input into the first terminal, a clock signal is input into the second terminal, and a data signal is input into the third terminal, and in a case of performing communication by the second interface circuit, the clock signal is input into the first terminal and the data signal is input into the third terminal.

Abstract: Described embodiments provide a system having a bridge for communicating information between two processor buses. The bridge receives a command from a first bus, the command having an identification field and an address field. As the command is entered into a buffer in the bridge, the address field is checked against one or more addresses. If there is a match, then control bits are checked to see if the command will be allowed or not depending on the identification field value. If the command is not transferred to the second bus, a flag is set in the buffer, and an error message is returned to the first bus, and an interrupt may be generated. The control bits allow commands access to specific addresses on the second bus or deny the access depending on the command identification field. Bit-wise masking provides a range of values for identification and address field matching.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a command from a first bus, the command having an identification field having a value. The command is then entered into a buffer in the bridge unless another command having the same identification field value exists in the buffer. Once the command with the same identification field value is removed from the buffer, the received command is entered into the buffer. Next, the buffered command is transmitted over a second bus. A response to the command is eventually received from the second bus, the response is transmitted over the first bus, and the command is then removed from the buffer. By not entering the received command until a similar command with the same identification value is removed from the buffer, command ordering is enforced even though multiple commands are pending in the buffer.

Abstract: Described embodiments provide a system having a bridge for connecting two different processor buses. A process monitor within the bridge allows for measuring latency of commands issued on a first bus, passing through the bridge, and executed by clients coupled to the second bus. By using identification fields associated with the command, measuring the latency of each command begins with matching the identification field of the command to an integer. As the bridge passes acknowledgements back to the first bus, the monitoring of the command is stopped when an identification field associated with an acknowledgement matches the identification field of the command being monitored. Data collected include the minimum, maximum, total latency, and the number of commands monitored. From this data, the average latency can be easily calculated.

Abstract: An improved industrial automation system and communication system for implementation therein, and related methods of operation, are described herein. In at least some embodiments, the improved communication system allows communication in the form of messages between modules in different control or enterprise domains. Further, in at least some embodiments, such communications are achieved by providing a communication system including a manufacturing service bus having two internal service busses with a bridge between the internal busses. Also, in at least some embodiments, a methodology of synchronous messaging is employed.

Abstract: The present invention is directed to a universal serial bus (USB) transaction translator and an associated IN isochronous transaction method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A register is used to record device bus information. Before the host sends an IN packet, the controller pre-fetches data from the device according to the device bus information and then stores the data in the buffers; the controller responds with the pre-fetched data to the host after the host sends the IN packet.

Abstract: A multi-interconnect integrated circuit device includes an input/output (I/O) circuit for conveying a plurality of interleaved data channel groups by configuring the I/O circuit to convey a first data channel group over a default fixed interconnect signal paths if there are no connection failures in the default fixed interconnect signal paths, and to convey the first data channel group over a second plurality of default fixed interconnect signal paths if there is at least one connection failure in the first plurality of default fixed interconnect signal paths, where the second plurality of default fixed interconnect signal paths includes a redundant fixed interconnect signal path for replacing a failed interconnect signal path from the first plurality of default fixed interconnect signal paths.

Abstract: A method for testing a serial over local area network (SOL) function of a motherboard of a computing device. The method determines that the SOL function is normal if forward data can be transmitted from the serial port of the motherboard to a network interface controller (NIC) of the motherboard through a predefined path, and backward data can be transmitted from the NIC to the serial port through a predefined reverse path. The method determines that the SOL function is abnormal if the forward data cannot be transmitted from the serial port to the NIC through the predefined path, or the backward data cannot be transmitted from the NIC to the serial port through the predefined reverse path.

Abstract: An electronic device includes a general purpose input output (GPIO) expander and a baseboard management controller (BMC). The GPIO expander includes a number of GPIO interfaces and a gathering interface connected to the GPIO interfaces. The BMC includes a public interface and a scanning interface connected to the gathering interface. Each element is connected to the public interface and a different one of the GPIO interfaces. The BMC periodically detects whether there is a signal input from the public interface, scans the GPIO interfaces when there is a signal input from the public interface to determine a GPIO interface with a logic high level, an element connected to the GPIO interface, and a signal input from the element, and records an event including the GPIO interface, the element connected to the GPIO interface, and the signal, and stores the event.

Abstract: Pluggable modules communicate via a switch fabric dataplane accessible via a backplane. Various embodiments are comprised of varying numbers and arrangements of the pluggable modules in accordance with a system architecture that provides for provisioning virtual servers and clusters of servers from underlying hardware and software resources. The system architecture is a unifying solution for applications requiring a combination of computation and networking performance. Resources may be pooled, scaled, and reclaimed dynamically for new purposes as requirements change, using dynamic reconfiguration of virtual computing and communication hardware and software.

Abstract: To discriminate whether a cable in conformity with a conventional standard or a cable in conformity with a new standard is connected. An HPD signal line (902) has, on an expanded HDMI sink apparatus (402) side circuit, a pull-up resistor (911) between the HPD signal line (902) and a voltage supply and a pull-down resistor (913) between the HPD signal line (902) and the ground, and a reserved line (903) has, on the expanded HDMI sink apparatus (402) side circuit, a pull-down resistor (914) between the reserved line (903) and a ground, and within a new HDMI cable (901), a pull-up resistor (912) between the reserved line (903) and a voltage supply of an expanded HDMI source apparatus (401). The expanded HDMI sink apparatus compares a voltage at a test point (19) on the reserved line (903) on the expanded HDMI sink apparatus (402) side with a reference voltage by using a voltage comparator (916).

Abstract: An interface apparatus, a cascading system thereof, and a cascading method thereof are provided. The cascading system includes a host, a first-type interface apparatus, and a second-type interface apparatus which are serially connected. The host provides data transmission of a first and a second channel by a first controller through a first interface port. In the first-type interface apparatus, data of the first channel is transmitted to a second controller through a second interface port and then to a third interface port, and data of the second channel is directly transmitted to the third interface port through the second interface port. In the second-type interface apparatus, the data of the second channel are transmitted to a third controller through a forth interface port and then to the fifth interface port, and the data of the first channel is directly transmitted to the fifth interface port through the forth interface port.

Abstract: Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame.

Abstract: A custom control system created based on combinations of software applications and hardware control and communication modules overlaid in a virtual backplane. The user can select the modules of interest and map them together without the loss of communications between the modules while the control system is configured and overlaid. The user can then archive the system design and implement the system with a greater level of confidence in the ability of the design to meet the requirements of the application while reducing the costs of the implementation.

Abstract: A connection expansion device connected to devices includes a plurality of ports to which devices are connected, a storage unit configured to record device information obtained from each port, and a processing unit configured to specify, based on the device information, a port in which an abnormal device exists, invalidate device information belonging to the port, and cause the storage unit to hold device information of a normal device.

Abstract: An extension device for connecting one or more peripheral devices to a computer, comprising a first bus for connecting to the computer; a second bus for connecting to the computer; a hub coupled to the first bus for connecting the computer to one or more peripheral devices; a controller for connecting the computer to a high-bandwidth device, the controller being switchably coupled to the hub and the second bus; and a switch for switching the controller, from being coupled to the hub, to being coupled to the second bus, when a connection to the computer is detected on the second bus.

Abstract: The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved.

Abstract: An image transmitting device for transmitting an image from an image source device to an image output device includes a second USB interface, an image receiver, a first memory, a wireless transmitter, a processor, and a switch. The image source device includes a first USB interface, and the image output device includes a wireless receiver. The second USB interface is connected to the first USB interface by a cable. The image receiver is used for receiving the image from the image source device. The first memory is used for storing the image received by the image receiver. The wireless transmitter is used for communicating with the wireless receiver and for transmitting the image from the first memory to the image output device. The switch is used for switching on or off the power voltage of the second USB interface and for driving the processor to switch on or off the image receiver.

Abstract: A computer docking station includes a wall having a first surface, a second surface, and an aperture extending through the wall. A securing member has a body portion configured to be positioned adjacent the first surface of the wall, and a securing projection coupled to the body portion. The securing projection is sized and configured to selectively extend through the aperture in the wall, beyond the second surface, and into a securement recess of a computer to secure the computer to the docking station. An adjustment mechanism is coupled with the body portion of the securing member and is operable to move the securing member relative to the wall between a first position, in which the securing projection is positioned to extend into a securement recess of the computer, and a second position, in which the securing projection is positioned to not extend into the securement recess.

Abstract: In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge.

Abstract: A multi-port memory device includes a plurality of serial I/O data pads for providing a serial input/output (I/O) data communication; a plurality of ports for performing the serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data communication with the ports; a plurality of first data buses for transferring first signals from the ports to the banks; a plurality of second data buses for transferring second signals from the banks to the ports; and a switching unit for connecting the first data buses with the second data buses in response to a control signal.

Abstract: A field bus network adapter includes a first field bus connection configured to connect a first field bus cable, a second field bus connection configured to connect a second field bus cable, and N number of third field bus connections configured to connect a third cable each. The first field bus connection and the second field bus connection are connected to the N number of third field bus connections such that (i) data received at the first field bus connection are output at a first of the N number of third field bus connections, (ii) data received at an nth of the N number of third field bus connections are output at an (n+1)th of the N number of third field bus connections, and (iii) data received at an Nth of the N number of third field bus connections are output at the second field bus connection.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.

Abstract: A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.

Abstract: A network system that is part of a main system includes: a first PCI express-network bridge with a first control unit and a first PCI express adapter terminating a first PCI express bus; and a second PCI express-network bridge connected to the first PCI express-network bridge through a network. The second PCI express-network bridge includes a second control unit and a second PCI express adapter terminating a second PCI express bus, wherein the first control unit detects a destination of a packet sent from the first PCI express adapter, searches a physical address of the destination from a packet encapsulating table, and encapsulates the packet in a frame so that the frame includes the physical address, and wherein the second control unit removes the encapsulation tagged to the packet, and transfers the packet to the destination through the second PCI express bus by referring to a PCI express configuration register.

Abstract: A method and data processing system enables scheduling of atomic operations within a Peripheral Component Interconnect Express (PCIe) architecture during page migration. In at least one embodiment, firmware detects the activation of a page migration operation. The firmware notifies the I/O host bridge, which responds by setting an atomic operation stall (AOS) bit to a pre-established value that indicates that there is an ongoing migration within the memory subsystem of a memory page that is mapped to that I/O host bridge. When the AOS bit is set to the pre-established value, the I/O host bridge prevents/stalls any received atomic operations from completing. The I/O host bridge responds to receipt of receipt of an atomic operation by preventing the atomic operation from being initiated within the memory subsystem, when the AOS bit is set to the pre-established value. The AOS bit is reset when the migration operation has completed.

Abstract: An object is to provide an information processing apparatus capable of improving the availability as a system while improving the reliability of a data transfer path and a data transfer method.

Abstract: The information processing system includes a plurality of information processing apparatuses connected via a network. Each apparatus includes one or more modules interconnected via a system bus. At least one of the modules is a network module having a network communication function. The information processing apparatus that inputs an external timing signal functions as a timing master, and the other information processing apparatuses function as a timing slave. The module in the timing master generates time synchronization information in the form of a packet and in the form of a command according to the timing signal and transmits the command to another module and transmits the packet to the timing slave via the network. The network module in the timing slave receives the packet from the timing master, converts the packet to the command to transmit to another module connected to the system bus and included in the timing slave.

Abstract: A method and structure(s) for providing a data path between and among nodes and processing elements within an interconnection fabric are described. More specifically, a device comprising a first circuit configured to couple between a first bus and a link is described. The circuit may be configured to operate as a bridge, support PCI configuration cycles, send outgoing information serially through the link in a format different from that of the first bus, and allow a host processor, communicating through the first bus, to selectively address one or more remote devices to which the device is configured to allow access. In some embodiments, the first circuit may support “spoof-proof” data protocols, and the device may operate in multiple modes including root bridge, leaf bridge, and gateway mode. Multiple addressing models may also be used.

Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Abstract: Bus transactions in a computer network are improved by utilizing a multicast transaction from a single initiator to multiple targets. The multiple targets simultaneously execute the transaction and provide a return transaction to the initiator. The transaction cycle time is reduced as individual request to each target is replace with a single request to a collective target group, addressable by a single base memory address. Interleaved read or write operation is provided to allow the multiple targets of a particular target group to independently execute a portion of the transaction request. Improved bus performance is achieve by utilizing the higher throughput capacity of the system bus providing a higher number of shorter data segments from each target executing its portion of the larger transaction.

Abstract: Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests—e.g. between those requestors providing the access requests—the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.

Abstract: According to an aspect of the embodiment, an input/output device transmits a message to a first node controller of a parent node which is set in advance via a cross bar. At this point, the cross bar generates information based on node information of the input/output device, and adds the generated information to the message. The first node controller transmits, via the cross bar, the message to a second node controller of a parent node corresponding to an input/output device that is to receive the message. The second node controller transmits, via the cross bar, the message to an input/output device that is to receive the message. At this point, the cross bar transmits the message restored by deleting the generated information from the message to the input/output device which is set as a destination.

Abstract: An interconnect coupled to a master device via at least two different connections is disclosed. In a particular embodiment, a system is disclosed that includes a first interconnect and a second interconnect coupled to the first interconnect. The first interconnect is coupled to a first master device via a single connection and the first interconnect is coupled to a second master device via at least two different connections. The second interconnect is coupled to a memory via a memory controller.

Abstract: A system includes a master device and multiple slave devices. The system also includes multiple bus interfaces forming a communication bus that couples the master and slave devices. Each bus interface includes a primary interface unit configured to communicate over first and second buses, where the first and second buses form a portion of the communication bus. Each bus interface also includes a secondary interface unit configured to communicate with the primary interface unit and to communicate with one of the slave devices over a third bus. Each bus interface further includes an isolator configured to electrically isolate the primary interface unit and the secondary interface unit. The primary interface unit is configured to receive multiple commands over the first bus, execute a first subset of commands, transmit a second subset of commands over the second bus, and transmit a third subset of commands over the third bus.

Abstract: A bus interconnect in accordance with present embodiments includes a via block having first and second interfaces separated by a conductive body, wherein the via block is configured to communicatively couple with a first bus through the first interface and wherein the conductive body is configured to extend through an opening in a bus support panel. A first coupling section of the jumper includes a first attachment feature, wherein the first attachment feature is configured to facilitate attachment with the second interface of the via block. A neck section of the jumper extends perpendicularly from the first coupling section, and a second coupling section of the jumper extends perpendicularly from the neck section in parallel with the first coupling section. The second coupling section includes a second attachment feature configured to facilitate attachment with a second bus. The first coupling section and the second coupling section each extend away from the neck section in different directions.

Abstract: A bridge system includes a request device, connected to a first bus; a target device, connected to a second bus; and a bridge, communicated with the first bus and the second bus, and the bridge has a buffer, wherein when the request device asks the bridge for reading data of a target address from the target device, a transaction is started, and the bridge asks the target device to transfer data of the target address and following addresses, and then the target device retrieves and transfers the data of the target address and following addresses to the bridge, that is stored in the buffer and then transferred to the request device in turn, and wherein as amount of transferred data to the request device reaches a threshold, the bridge continuously asks data of a following address of the target device before the transaction is finished.

Abstract: A storage system including: a storage apparatus including a plurality of storage devices on which a plurality of logical units is configured and a first controller that controls accesses to the plurality of logical units; and a file server coupled to said storage apparatus and including a second controller and a memory storing management information which indicates relationships between each of the plurality of logical units and each of a plurality of indicators; wherein the first controller, in response to a request to create a first folder with a first indicator, creates the folder on one or more first logical units included in the plurality of logical units, the one or more first logical units related to the first indicator.

Abstract: A monitor for a computer includes a display screen, a frame fixing the display screen, a display circuit, a personal system (PS)/2 keyboard interface, a power circuit, and a monitor video interface. The PS/2 keyboard interface is disposed on the frame, and includes a data signal pin, a clock signal pin, a power pin, and a ground pin. The power circuit powers the display circuit and the PS/2 keyboard interface. The monitor video interface includes video pins, first and second idle pins. The video pins are connected to the display circuit. The first idle pin is connected to the data signal pin. The second idle pin is connected to the clock signal pin.

Abstract: In an embodiment, a translation of a hierarchical MMIO address range to a physical MMIO address range and an identifier of a bridge in a south chip are written to a north chip. A transaction is received that comprises a hierarchical MMIO address. The hierarchical MMIO address that is within the hierarchical MMIO address range is replaced in the transaction with the identifier of the bridge and with a physical MMIO address that is within the physical MMIO address range in the south chip. The transaction is sent to the device that is connected to the bridge in the south chip. The physical MMIO address range specifies a range of physical MMIO addresses in memory in the device.

Abstract: A communication function between ports on a node that does not require a common time base to be distributed across the network is disclosed. A data stream received over a first port is placed on an interface between nodes using the time base of the first port; a second port samples the data stream on the interface and timestamps it using the time base of the second port. The data stream is timestamped by the second port and packetized before transmitted to the second node to another bridge or device. Alternatively, the first port extracts a time stamp from the data stream and calculates an offset using a cycle timer value from the bus connected to the first port. The offset is added to the cycle timer value on the bus connected to the second port and used to timestamp the data stream.

Abstract: A system LSI includes first and second memories, first and second buses, a bus bridge that performs signal transfer between the first and second buses, a first bus system connecting to the first bus and accessing the first or second memory, a second bus system connecting to the second bus and accessing the first or second memory, a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses and first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories.

Abstract: A processor-memory bus comprises a command portion for transmitting addresses and commands, having a unidirectional input portion for transmitting commands to a central repeater unit, and a unidirectional broadcast portion for broadcasting commands from the repeater. The input portion comprises a plurality of links running from different devices, wherein each link is less than the full width of the broadcast bus portion. A command is transmitted over the input portion in a plurality of bus cycles, and broadcast over the broadcast portion in a single bus cycle. Since multiple input links connect to the central command repeater, it is possible to keep the broadcast bus full notwithstanding the fact that multiple bus cycles are required to transmit an individual command on the input portion. Preferably, the links are arranged hierarchically, from processors to local repeaters, from local repeaters to the central repeater, and back again.