Abstract: An external memory based FIFO (xFIFO) apparatus coupled to an external memory and a register bus is disclosed. The xFIFO apparatus includes an xFIFO engine, a wDMA engine, an rDMA engine, a first virtual FIFO, and a second virtual FIFO. The xFIFO engine receives a FIFO command from the register bus and generates a writing DMA command and a reading DMA command. The wDMA engine receives the writing DMA command from the xFIFO engine and forwards an incoming data to the external memory. The rDMA engine receives the reading DMA command from the xFIFO engine and pre-fetches a FIFO data from the external memory. The wDMA engine and the rDMA engine synchronize with each other via the first virtual FIFO and the second virtual FIFO.

Abstract: A position sensing system controls selection of channels in a KVM switch having a plurality of channels. The system has a sensor interface for receiving a sensor reading indicating a current position of a position movable component. Each position of the movable component is associated with one of the plurality of channels. The position sensing system also includes a position component for selecting channels of the KVM switch according to the sensor reading. The position component comprises a position definition component and a translation component. The definition component identifies one of the channels corresponding to the sensor reading based on one of a position definition. Each position definition provides sensor readings corresponding to the positions associated with one of the channels. The translation component generates a signal for selecting the determined channel at the KVM switch. This signal is provided to the KVM switch to switch the KVM channel.

Abstract: A method for managing a subnet in a computer system, comprising: providing a bus adaptor which is engaged with a notch of a PCIE bus in a computer system, wherein the computer system comprises a plurality of subnet nodes, each subnet node comprises a node control chip and at least one Central Processing Unit (CPU), each subnet node is connected to the PCIE bus, the PCIE bus connects the respective subnet nodes through an IB switchboard to construct a subnet; providing, by the bus adaptor, a network address of each subnet node; and performing communications between the subnet nodes according to the network address of each subnet node provided by the bus adaptor.

Abstract: Disclosed are methods, circuits and systems for wireless transmission of a video signal from a computing platform. There is provided a video and/or audio signal source device such as a laptop computer. The video and/or audio signal source device may include a Display Mini Card (DMC) System Connector. The video and/or audio signal source device may include a Mini Card (HMC or FMC) System Connector, and/or a Display Port (DP) connector. There may be provided a Display Mini Card (DMC) or a Mini Card (FMC or HMC) which may include electrical circuits adapted to receive video and/or audio signals from the DMC System Connector or the DP connector of the video and/or audio signal source device. Received video and/or audio signals may be transmitted to a functionally associated video/audio receiver. The electrical circuits of the Display Mini Card (DMC) or the Mini Card (FMC or HMC) may be adapted to transmit a video and/or audio signal using a video link such as WHDI, WIFI DIRECT or WIFI DISPLAY.

Abstract: A data storage apparatus having improved data transfer performance. The storage apparatus has: plural controllers connected to each other by first data transfer paths; plural processors controlling the controllers; and second data transfer paths through which the controllers send data to various devices. Each of the controllers has a data-processing portion for transferring data to the first and second data transfer paths. The data-processing portion has a header detection portion for detecting first header information constituting data, a selection portion for selecting data sets having continuous addresses of transfer destination and using the same data transfer path from plural data sets such that a coupled data set is created from the selected data sets, a header creation portion for creating second header information about the coupled data set, and coupled data creation means for creating the coupled data set from the selected data sets and from the second header information.

Abstract: To make it possible to take over an IO configuration that is assigned to logical partitions in reallocation of the logical partitions, and to make an IO access work normally. A computer system has a server having an IO bridge, a switch that has a first IO bridge for connecting with the IO bridge of the server through a bus and plural second IO bridges for connecting to plural IO devices through a bus, and bus number assignment management means for fixedly assigning mutually different PCI bus numbers to the plural second IO bridges.

Abstract: An HVAC data processing and communication network includes a subnet controller and at least one demand unit. A bus interface device associated with the demand unit is configured to receive a demand message from the subnet controller over the network. The bus interface device controls an operation of said demand unit in response to said demand message.

Abstract: A SAS expander forms a first path coupling the SAS initiator and a first port of a SAS target together. The first SAS expander notifies the SAS initiator of a virtual expander address instead of a SAS address of the first SAS expander. The first SAS expander notifies the SAS initiator of a virtual target port address, at least instead of a SAS address of the first port of the SAS target. A second SAS expander forms a second path coupling the SAS initiator and a second port of the SAS target together. The second SAS expander notifies the SAS initiator of the virtual expander address instead of a SAS address of the second SAS expander. The second SAS expander notifies the SAS initiator of the virtual target port address, at least instead of a SAS address of the second port of the SAS target.

Abstract: In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.

Abstract: Methods and apparatuses that utilize a serial bus, such as a universal serial bus (USB), for communications between a communications network, a computing device, and an auxiliary device are disclosed. Some embodiments comprise methods handling sideband communications using serial buses. One or more of the embodiments comprise differentiating in-band data from out-of-band data, transferring information of the in-band data between a communications network and a computing device, and transferring information of the out-of-band data between the communications network and an auxiliary device. Some embodiments comprise an apparatus having a communications network interface, an auxiliary device interface, and a computing device interface. Of the interfaces, one or more may be a serial bus interface. The apparatus may differentiate between in-band and out-of-band data and communicate information of the out-of-band data to an auxiliary device. In some embodiments, the apparatus may also transfer control information.

Abstract: A bus control circuit includes a first bus to which a first circuit is connected, a second bus to which a second circuit is connected and a control circuit that transfers data between the first circuit and the second circuit, wherein the control circuit monitors completion of the processing of an access request that is resident in the control circuit.

Abstract: In a printing system or method, two printing units apply printing ink onto a recording material, each printing unit having multiple apparatuses with a respective microprocessor controller. The microprocessor controllers are connected with one another via a respective data bus segment and each data bus segment has multiple data lines. The two data bus segments of the two printing units are connected with a bus switch. The bus switch has a data switch to connect a respective one of the lines of the one data bus segment with the corresponding line of the other data bus segment, a respective terminating resistor being provided for each data bus segment. The terminating resistors are connected with a respective terminating switch coupled with the data switches such that either all terminating switches are open and all data switches are closed, or all terminating switches are closed and all data switches are open.

Abstract: A storage system provides a modular interface-independent architecture. The storage system includes multiple of storage devices removably coupled to a backplane. The backplane is configured to receive the signals from the storage devices, and separate the received signals into groups of power and data signals. The backplane is further configured to modify the second data signals to include information describing storage devices associated with the data signals, and convert the data signals into a predetermined interface technology signal format. The storage system also includes a bridge configured to modify the converted data signals to remove information describing storage devices associated with the data signals. The bridge is further configured to group the modified converted data signals into multiple data blocks and assign each of the plurality of data blocks to an output port of the bridge.

Abstract: Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.

Abstract: Systems and methods of sharing legacy devices in a multi-host environment are disclosed. An exemplary method for sharing legacy devices in a multi-host environment includes receiving device information from a legacy device, the device information identifying a target within a virtual machine. The method also includes encapsulating the device information into a corresponding bus transaction for a network switch fabric. The method also includes routing the bus transaction over the network switch fabric in the virtual machine to a host within the virtual machine.

Abstract: An apparatus and method of emulating a hardware accelerator engine over an interconnect link such as PCI Express (PCIe) link. In one embodiment, the accelerator emulation mechanism is implemented inside a PCIe Host Bridge which is integrated into a host IC or chipset. The accelerator emulation mechanism provides an interface compatible with other integrated accelerators thereby eliminating the overhead of maintaining different programming models for local and remote accelerators. Co-processor requests issued by threads requesting a service (client threads) targeting remote accelerator are queued and sent to a PCIe adapter and remote accelerator engine over a PCIe link. The remote accelerator engine performs the requested processing task, delivers results back to host memory and the PCIe Host Bridge performs co-processor request completion sequence (status update, write to flag, interrupt) include in the co-processor command.

Abstract: A custom control system created based on combinations of software applications and hardware control and communication modules overlaid in a virtual backplane. The user can select the modules of interest and map them together without the loss of communications between the modules while the control system is configured and overlaid. The user can then archive the system design and implement the system with a greater level of confidence in the ability of the design to meet the requirements of the application while reducing the costs of the implementation.

Abstract: A communication module for connecting a serial bus, which transmits data in packets, to a plurality of system buses of a gateway, which transmit data word by word, the communication module having a communication protocol unit, which is connected to the serial bus, for converting between data packages and messages, which are respectively made up of a plurality of data words, a message relaying unit for relaying messages between at least one message memory and the communication protocol unit, as well as buffer memories, a plurality of interface units, which are respectively connected to an associated system bus of the gateway, each interface unit being connected to at least one associated buffer memory, which stores a message temporarily, a transmission of data words via a plurality of system buses and their associated interface units from and to the buffer memories of the interface units taking place simultaneously, without delay.

Abstract: A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus (USB) cable having at least an ID pin and a VBUS pin. The PHY is also to communicate with an ACA-agnostic USB controller configured to act as an A-device or as a B-device. The ACA includes a USB accessory port. The ACA bridge circuit includes detection and control logic configured to detect, based on a resistance sensed on the ID pin, that a B-device is connected to the USB accessory port of the ACA and, as a result of such a detection, generate a signal to the USB controller that causes the USB controller to act as an A-device and ignore a VBUS drive signal from the USB controller.

Abstract: A method is disclosed in which data is exchanged via a bus coupler (500) between a network (410) designed for transmitting Ethernet telegrams and a lower-level bus system (420), wherein the bus coupler (500) is connected via a first interface (520) to the network (410) and via a second interface (530) to the lower-level bus system (420), and wherein process data is read in and/or output through at least one bus node (610, 620, 630) of the lower-level bus system (420). Furthermore, a bus coupler (500), a bus node (610, 620, 630), and a control system (10) that are designed for execution of the method are disclosed.

Abstract: Methods and apparatus, including computer program products, implementing techniques for forming an Advanced Switching (AS) packet by applying AS path binding information to a packet received over a Peripheral Component Interconnect-Express (PCIe) fabric according to a downstream port identifier associated with the packet, and sending the AS packet to an AS fabric. Methods and apparatus, including computer program products, implementing techniques for processing an AS packet received over an AS fabric by comparing an AS payload of the AS packet with one or more memory spaces associated with port identifiers, determining whether the AS payload comprises a base packet to be transmitted to the PCIe fabric based on the comparison, and if so, removing an AS header from the AS packet to reveal the base packet.

Abstract: A method for interfacing an out-of-order bus and multiple ordered buses and a bus bridge. The bus bridge includes multiple ordered bus interfaces, where each ordered bus interface is coupled to an ordered bus. A flow control logic circuit is coupled to the out-of-order bus and to the multiple ordered bus interfaces. The flow control logic circuit controls a flow of transaction requests between the out-of-order bus and each of the ordered buses interfaces. The flow control logic circuit includes an updating circuit for updating dependency resolution attributes and data readiness attributes associated with transaction requests, and a shared memory unit for storing the dependency resolution attributes, the data readiness attributes and the transaction requests where the transaction requests are destined to the ordered buses.

Abstract: Degradation of data transfer performance is restrained during data transfer for mirroring between first and second controllers. The first and second controllers are connected with a first path for connecting a second port of a first switch unit on the first controller to a second port of a first switch unit on the second controller, and with a second path independent of the first path, for connecting a second port of a second switch unit on the first controller to a second port of a second switch unit on the second controller.

Abstract: A module is provided for installation in a drive bay of a computer and is adapted to accommodate expansion circuitry rather than the electromechanical devices conventionally installed in drive bays. A system interface board is provided for insertion into an expansion socket on the computer's motherboard and is connected to the module, thus interfacing the expansion circuitry to the computer. The expansion circuitry can be greater in volume and is more accessible and more easily cooled than expansion circuitry installed in expansion sockets on the motherboard.

Abstract: Methods and apparatus for improved performance in communications with a SATA target device. Features and aspects hereof provide for continuing DMA transfers from a storage controller (e.g., a SATA host or a SAS/STP initiator) to a SATA target device without regard to receipt of DMA ACTIVATE Frame Information Structures (FIS). Logic to implement these features may be provided by bridge logic within an enhanced SAS expander coupled with an enhanced SAS/STP initiator or may be provided by suitable logic in an enhanced SATA host coupled directly with an enhanced SATA target device. By continuing DMA transfer of data from the initiator/host to the SATA target device without regard to receipt of a DMA ACTIVATE FIS, more of the available bandwidth of the SAS/SATA communication link may be utilized. Other standard features of the SAS/SATA protocols provide for flow control to prevent overrun of the SATA target device's buffers.

Abstract: Microprocessors with multi-core dies that include bypass buses are provided. Each microprocessor comprises a plurality of physical pins for coupling the microprocessor to a processor bus coupled to a chipset. The multi-core die has at least two complementary sets of one or more processing cores, each providing a bus interface coupling respective core inputs and outputs to corresponding processor bus lines. A bypass bus on the die enables cores of the complementary sets to bypass the processor bus and communicate directly with each other. The bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-drive signals from the processor bus. Moreover, the microprocessor is operable to detect whether the chipset or a complementary core is driving the processor bus, and if the latter, to select the higher quality bypass bus signals over the corresponding processor bus signals.

Abstract: A system and method are disclosed for processing commands to network target devices through a SCSI router in a Fiber Channel network having a plurality of Fiber Channel hosts. The system and method are implemented in the SCSI router and include receiving a command from one of the plurality of Fiber Channel hosts and, if the command is for a transfer of data larger than a threshold size, streaming the data to the target device. If a preset size memory block is free, a data block is requested from the Fiber Channel host that issued the command. Otherwise, the method of this invention waits to request the data block until the preset size memory block is free. The SCSI router receives the data block and stores the data block in a FIFO queue. The method of this invention repeats until an initial number of data blocks are stored in the FIFO queue. The command and the first data block received are forwarded to the network target device.

Abstract: Embodiments may include two gigabit Ethernet controllers integrated within a single chip and an I/O bridge coupled to the two gigabit Ethernet controllers and integrated within the single chip. The system may further include an I/O function coupled to the I/O bridge that is integrated within the single chip. The I/O function may include I/O logic and an I/O buffer integrated within the single chip and coupled to the I/O bridge and/or the two gigabit Ethernet controllers. A timing function or timing block may also be coupled to the I/O bridge and integrated within the single chip. A host system may be coupled to the I/O bridge. The I/O bridge may further include a primary bus controller, which may be a primary PCI bus controller. The controller or controller block may include control and status registers that may be coupled to the primary bus controller.

Abstract: An integrated circuit device may include a mask register that stores mask values writable from a processor interface; and mask logic that selectively masks status indications from each of a plurality of buffers according to stored mask values; wherein the buffers alter the status indications in response to accesses from at least one different interface other than the processor interface.

Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.

Abstract: An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the chip side port. The interface is constructed so that interrupt signals from an off-chip circuit can be conveyed on-chip in a manner such that the interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to an on-chip communication path. The same principle is applicable to power-down signals.

Abstract: A data processing system includes an input/output (I/O) host bridge to which at least one I/O adapter is coupled by an I/O link. In a register of the I/O host bridge, a configuration partitionable endpoint (PE) field is set to identify a PE to be used for an I/O configuration operation. Thereafter, the host bridge initiates the I/O configuration operation on the I/O link and determines if an error occurred for the I/O configuration operation. In response to a determination that an error occurred for the I/O configuration operation, an error state is set in the I/O host bridge only for the PE indicated in the configuration PE field of the register in the I/O host bridge, wherein I/O configuration errors are isolated to particular PEs.

Abstract: A semiconductor device includes: a first transistor; a second transistor; an interlayer insulating film covering the transistors; a rectangular-shaped first bus formed on the interlayer insulating film and connected to first source/drain regions; a rectangular-shaped second bus formed on the interlayer insulating film with spacing from the first bus and connected to third source/drain regions; an inter-bus interconnect formed between the first and second buses for connecting these buses; a first contact pad provided on the first bus, to which a wire is connected; and a second contact pad provided on the second bus, to which a wire is connected. The inter-bus interconnect is in contact with part of the side of the first bus facing the second bus and part of the side of the second bus facing the first bus. The first and second contact pads are respectively in contact with part of the first and second buses.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BICS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: A custom control system created based on combinations of software applications and hardware control and communication modules overlaid in a virtual backplane. The user can select the modules of interest and map them together without the loss of communications between the modules while the control system is configured and overlaid. The user can then archive the system design and implement the system with a greater level of confidence in the ability of the design to meet the requirements of the application while reducing the costs of the implementation.

Abstract: A device, method, and system are disclosed. In one embodiment the device includes a first virtual machine to directly access a physical audio codec. The device also includes a virtual audio codec that is managed by the first virtual machine. The virtual audio codec can provide a custom interface to the physical audio codec for one or more additional virtual machines apart from the first virtual machine.

Abstract: A system-on-a-chip (SOC) bridge is described that applies an adapted delay, or latency, to data transfers across the bridge to avoid data corruption without reducing data transfer performance. The adapted delay assures that a source SOC service device transferring data to a destination SOC service device via the bridge and an SOC crossbar bus does not prematurely assume that the data transfer is complete upon transferring the data to the bridge. The bridge causes wait states to be inserted into the transfer between the source SOC service device and the SOC bridge until the SOC bridge receives confirmation that the data has arrived at the destination SOC service device. The adapted delay assures that subsequent operations are not prematurely initiated by the source SOC service device and/or the SOC CPU that may interfere with the data transfer from the SOC bridge to the destination SOC service device, resulting in corrupted data.

Abstract: A portable data processing system includes a handheld communication device and a signal input/output device. The signal input/output device includes a casing, communication module, an input module, an output module and a bridging unit. The input module is used for generating and outputting a control command. When the handheld communication device is accommodated within the receiving space and connected with the communication module, the handheld communication device is operated according to the control command. The output module is used for outputting a data signal generated by the handheld communication device in real time.

Abstract: An improved interface technique for use in a southbridge or I/O hub or in similar devices is provided where non-posted read requests are received from at least one requestor, and upstream commands based on these requests are transmitted. Response data is received in reply to commands that were previously transmitted, and responses are transmitted to the at least one requester based on the response data. A buffer unit is provided for storing command identification data that identifies commands that were already transmitted or that are still to be transmitted, and response availability data that specifies response data that has been received by the receive engine. The improvement may enable multiple outstanding read requests.

Abstract: An embodiment of a technique to transfer data between two different interfaces is disclosed. The embodiment of the technique includes: manipulating data arriving at a first data interface with a first word width into data with a second word width; transferring the manipulated data to a second data interface having the second word width; and selecting one of a plurality of different word widths for one of the first or second word widths.

Abstract: A wireless protocol may be implemented in a smart transceiver device that contains the physical (PHY) and media access control (MAC) layers of the wireless protocol stack. In various embodiments, a serial peripheral interface (SPI) based design may be used. Disclosed is an embodiment of a protocol which may be used to provide control and data transfer to and from the smart transceiver. In particular, an exemplary format of the protocol, the commands, and responses is disclosed. In a further embodiment, an application programming interface (API) is disclosed. The API may provide hardware independent services that can be used to establish, maintain, and transport data to and from the system and the smart transceiver device. In particular, an exemplary and non-limiting set of services, function calls, configuration methods, events, and parameters is disclosed.

Abstract: A controller is provided that receives a single enclosure management (EM) serial bit stream from an expander or other device and divides the EM serial bit stream into multiple EM serial bit streams for delivery to multiple respective midplanes or backplanes. In this way, a separate EM serial bit stream is provided to each midplane or backplane without having to increase the number of ports that are available on the expander or other device that interfaces with the backplane or midplane.

Abstract: A device receives a standard command. The device judges whether an address field and/or a data length field and/or a data field of the standard command includes at least one of a vendor command, a vendor data and a checkword. The device judges whether the address field and/or a data length field and/or the data field of the standard command matches a vendor predetermined pattern. If matched, the device performs a vendor operation based on the vendor command and/or the vendor data of the standard command.

Abstract: A one-way bus bridge pair that transfers secure data in one direction, the bus bridge pair including a transmitting bus bridge, a receiving bus bridge, and a link. The link can connect the transmitting bus bridge and receiving bus bridge. The transmitting bus bridge may be arranged not to receive any data from the receiving bus bridge, and the receiving bus bridge may be arranged not to send any data to the transmitting bus bridge.

Abstract: A processing system includes a plurality of first circuit modules. A plurality of second circuit modules are coupled to an RF data bus via intra-device RF communications. The RF data bus receives first data from at least one of the plurality of first circuit modules, and transmits the first data via intra-device RF communications to at least one of the plurality of second circuit modules.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: A configurable register method and structure included configuration logic to form a register value. A data bridge system, for connecting an interface of a computer system to a plurality of application-specific integrated circuits (ASIC), has a data bridge operatively coupled between the computer interface and the plurality of ASICs that employs the configurable registers. The data bridge has a read only memory for storing at least the initial values and mask values for each ASIC of the plurality of ASICs. The data bridge upon initialization forms base address registers and other configuration data that are queried by the computer system. When the ASICs are graphic processors, the initial values and the mask values stored in the read only memory define the base address registers in the data bridge as a function of the configuration requirements of the graphic processors. The base address registers are thus programmable as a function of the initial values and mask values in the read only memory.

Abstract: A method and apparatus to use Solid State Drives (SSD) in a high availability enterprise system is provided. Concurrent redundant paths are provided to the SSD to at least two storage controllers via a serial system bus using a non-storage bus protocol.

Abstract: A motherboard includes an I/O chip, a south bridge chip, and a delay circuit. The I/O chip detects a standby voltage on the motherboard and outputs an indicating signal that indicates whether the standby voltage is at high level. The south bridge chip is connected to the I/O chip to receive the indicating signal. The delay circuit is connected to the I/O chip and the south bridge chip. The delay circuit delays the indicating signal before sending the indicating signal to the south bridge chip.

Abstract: Communications adapters and methods are provided for interfacing communications for an EtherNet/Ip or other general purpose industrial network, a Fieldbus or other open protocol device network, and a PointBus or other proprietary network. The adapter may be integrated in a module of a backplane system with connections to the general purpose, proprietary, and open protocol device networks, and provides a bridging for communications across the networks to make devices on the proprietary and open protocol networks accessible as if they were on a single device network and with sequential addressing capabilities.