Abstract: One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

Abstract: Multi-rank memories and methods for self-refreshing multi-rank memories are disclosed. One such multi-rank memory includes a plurality of ranks of memory and self-refresh logic coupled to the plurality of ranks of memory. The self-refresh logic is configured to refresh a first rank of memory in a self-refresh state in response to refreshing a second rank of memory not in a self-refresh state in response to receiving a non-self-refresh refresh command for the second rank of memory.

Abstract: An electronic device includes a memory control circuit that controls a DRAM, and the memory control circuit performs: a first distributed refresh process for issuing refresh commands to the DRAM at a predetermined interval so that storage elements of which the DRAM is configured are refreshed at least once in a predetermined period Ts; a concentrated refresh process for issuing, triggered by a predetermined request to the DRAM, a predetermined number of times Nc of the refresh commands in a burst at an interval that is shorter than the predetermined interval; and a second distributed refresh process for, when the predetermined number of times Nc of refresh commands have been issued, calculating a refresh interval Tr for refreshing remaining storage elements that have not yet been refreshed in the predetermined period Ts and issues refresh commands at the calculated refresh interval Tr.

Abstract: A refresh controller transmits two refresh request signals of a first request signal which indicates a time at which a refresh operation of a DRAM may be performed and a second request signal which indicates a time at which a refresh operation of the DRAM must be performed, to an arbitrator. On the other hand, also transfer request signals each of which requests a data transfer are transmitted from plural data transfer parts, respectively, to the arbitrator. If no transfer request signal is input when a first request signal is input to the arbitrator, a refresh operation of the DRAM is performed. As a result, a refresh operation is performed when the crowding level of a bus is relatively low. This improves an efficiency in a data transfer.

Abstract: One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

Abstract: A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.

Abstract: A semiconductor memory device capable of performing a partial self refresh and semiconductor memory system including same is provided. The semiconductor memory device includes: a memory circuit including a memory array; a skip address storage unit storing an address of an excluded region not requiring refresh in the memory array as a skip address; a refresh address generator providing an address of a region of the memory array requiring refresh as a refresh address; and an address comparator receiving and comparing the skip address and refresh address, and providing a refresh control signal to the memory circuit based on the comparison.

Abstract: A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly scheduled refresh can be skipped in response to detecting a request for the regularly scheduled refresh.

Abstract: According to one embodiment, a storage control device includes a controller, a detector, and a refreshing module. The controller writes image data, which is to be output to a display module, to a storage device and outputs the image data from the storage device to the display module. The detector detects a blanking period during which the controller does not write the image data to the storage device and does not output the image data from the storage device to the display module. The refreshing module refreshes the storage device by rewriting the image data to the storage device at a predetermined time interval if the detector detects a blanking period.

Abstract: Systems and methods for determining a refresh rate of volatile memory are provided. In this regard, a representative system, among others, includes a radio frequency (RF) device; a computing device that communicates with the RF device, the computing device including a refresh manager that monitors activities of the RF device; and volatile memory that communicates with the refresh manager of the computing device, wherein the refresh manager determines a refresh rate of the volatile memory based on the monitored activities of the RF device. A representative method, among others, for determining the refresh rate of volatile memory, includes monitoring activities of a radio frequency (RF) device; and adjusting a refresh rate of volatile memory based on the monitored activities of the RF device.

Abstract: A technique for efficiently preserving the ordering of data being written to a nonvolatile memory through a subsystem of a network storage system in the event of a power disruption, where the subsystem does not inherently guarantee that the ordering of the data will be preserved. The subsystem can be, for example, a memory controller hub. During normal operation of the system, data is written to the nonvolatile memory without flushing the data to the nonvolatile memory. In response to a power disruption in the system, data sources in the system that can initiate write transactions destined for the nonvolatile memory are inhibited from initiating write transactions destined for the nonvolatile memory, and pending write data within the subsystem is allowed to be committed to the nonvolatile memory. The nonvolatile memory is then placed into a self-refresh state.

Abstract: Non volatile storage may be employed to temporarily store data which is destaged to data storage drives. The non volatile storage is configured to preserve the data through a power outage. Some data may be preserved, but is not needed, such as the result of a failover to another non volatile storage. This unneeded data is tested to verify the non volatile storage by indicating whether the data survived the power cycle from full power to self refresh mode battery power to full power, without risking the loss of data that is needed.

Abstract: A method and system for refreshing DRAM having a plurality of banks, each of the banks including a plurality of rows includes dividing all banks in DRAM into a plurality of groups of banks, each of the groups having n banks, wherein n is an integer greater than or equal to 1. A threshold of available retention time for each group of banks is determined. Each row of banks in each group of banks is refreshed. Refreshing one row of a bank in one group of banks includes determining whether a refresh operation for the row of the bank conflicts with an access operation for the bank where the row of the bank is located. If there is a conflict, then it is determined whether to perform the refresh operation or the access operation for the current row of the bank. If it is determined to perform the access operation, the access operation is continued. If it is determined to perform the recess operation, the current row of the bank is refreshed. DRAM access performance is improved.

Abstract: In a directed auto-refresh (DARF) mode, refresh commands are issued by a controller, and refresh row and bank addresses are maintained internally to a memory module. A bank address counter internal to the memory is initialized to a first predetermined value upon entering DARF mode. The memory refreshes the currently addressed bank in response to a DARF command, and increments the bank address counter in a predetermined sequence. The controller tracks the bank address, and may issue one or more memory access commands while a DARF operation is being performed, if the memory access and the refresh are directed to different banks. Upon exiting a self-refresh mode, the bank address counter assumes a second predetermined value. The second predetermined value may be fixed, or may be n+1, where n is the value of the bank address counter when self-refresh mode is initiated.

Abstract: A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the time interval between successive memory refresh operations is relatively long, as compared to the time interval between successive memory refresh operations in a conventional volatile memory device, such as a DRAM. A processor can perform periodic memory refresh operations by executing a set of memory refresh instructions implemented in software, rather than in hardware. Accordingly, the memory device can advantageously be simplified, because the need for memory refresh circuitry and for a unique refresh control signal are advantageously eliminated. Moreover, the processor executing the memory refresh instructions can typically perform more sophisticated algorithms, as compared to memory refresh circuitry implemented in hardware, for determining when to perform a memory refresh operation.

Abstract: A disk drive is disclosed including a disk comprising a plurality of refresh zones, and a head actuated over the disk. The disk drive further comprises control circuitry for receiving access commands from a host. The control circuitry refreshes a refresh zone in a plurality of segments with an interval between each segment, and processes at least one of the access commands during the interval between at least two of the segments, wherein a size of each segment and the interval ensures an average throughput of access commands received from the host does not fall below a first threshold.

Abstract: A method for refreshing memory is provided. The method comprises determining when a first memory of a plurality of memories is not being accessed and sending a refresh opportunity command from a master refresh controller to one of a plurality of local refresh controllers when the first memory is not being accessed, wherein the one of a plurality of local refresh controllers controls only the first memory. The method further comprises determining when the first memory needs refreshing and refreshing the first memory.

Abstract: A renewal of an internal address generated by an internal address generator that is used for a refresh operation of information in a memory unit including a plurality of memory cells is preformed during a refresh operation before an activated word line connected to the memory cell corresponding to the internal address is inactivated in the refresh operation.

Abstract: Embodiments of apparatuses, methods, and systems for decoding a virtual machine control structure identification are disclosed. In one embodiment, an apparatus includes a virtual machine control structure to decode a virtual machine control structure identification data. The virtual machine control structure identification data is decoded into an address of a virtual machine control structure field and an offset. The offset is to help identify a micro-operation associated with a virtual machine architecture instruction to be executed.

Abstract: In one embodiment, a processor comprises a plurality of registers configured to store processor state and an execution core coupled to the registers. The execution core is configured, during a switch between processor execution of a guest and processor execution of a virtual machine manager (VMM) that controls the guest, to save only a portion of the processor state to a memory. In another embodiment, a method comprises switching from processor execution of a first one of a guest and a virtual machine manager (VMM) to processor execution of a second one of the guest and the VMM, wherein the VMM controls execution of the guest; and during the switching, the processor saving only a portion of a processor state to memory.

Abstract: A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly scheduled refresh can be skipped in response to detecting a request for the regularly scheduled refresh.

Abstract: To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation.

Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

Abstract: A semiconductor integrated circuit according to an aspect of the invention includes a plurality of master devices which issue data transfer requests, at least one slave device which performs data transfer in accordance with the data transfer requests, and a network which arbitrates the plurality of data transfer requests respectively issued from the plurality of master devices, and informs the slave device of the arbitration result, thereby performing data transfer between the master devices and the slave device, wherein when issuing the data transfer request, the master device informs the network of a period which extends from the issuance of the data transfer request to the start of the data transfer.

Abstract: A calibration operation can be performed automatically at a semiconductor device without issuing a calibration command from a controller. Because a calibration operation is performed in response to a fact that the auto refresh command has been issued for a predetermined number of times, a periodical calibration operation can be secured and a read operation or a write operation is not requested from a controller during a calibration operation.

Abstract: Systems and methods to respond to error detection are provided. First data may be received at a first memory controller port in response to a read command issued from the first memory controller port. The read command may be issued as a second read command from a second memory controller port after determining that the first data contains a first uncorrectable error. Second data may be received at the second memory controller port in response to the second read command. A repair write command may be issued from the first memory controller port after determining that the second data does not contain any errors. The repair write command may initiate writing the second data from the first memory controller port.

Abstract: In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.

Abstract: A clock enable (CKE) control circuit (112) is provided between a memory control circuit (111) and a SDRAM (120). When a system is in, e.g., a sleep state, the CKE control circuit (112) controls a CKE signal outputted to the SDRAM (120) such that it is fixed to a Low level. As a result, it is possible to halt a power supply provided to the memory control circuit (111), while maintaining the low-power-consumption mode of the SDRAM (120), so that power consumption resulting from a leakage current is suppressed. In addition, it becomes also possible to reset the memory control circuit (111), while maintaining the low-power-consumption mode of the SDRAM (120).

Abstract: A method for implementing prioritized refresh of a multiple way, set associative DRAM based cache includes identifying, for each of a plurality of sets of the cache, the existence of a most recently used way that has not been accessed during a current assessment period; and for each set, refreshing only the identified most recently used way of the set not accessed during the current assessment period, while ignoring the remaining ways of the set; wherein a complete examination of each set for most recently used ways therein during the current assessment period constitutes a sweep of the cache.

Abstract: A controller and a memory subsystem including a plurality of memory banks each having a plurality of memory devices, in which the controller includes a memory device configured to store an identification (ID) of each of the plurality of memory banks; and a control logic configured to read an ID of a memory bank to be accessed among the plurality of memory banks from the memory device, then output the ID, and then output a command. Each of the plurality of memory devices includes an input port, a register configured to store an ID of each memory device, and a determination circuit configured to receive and compare an ID input via the input port with the ID stored in the register and to generate a control signal according to a result of the comparison. The input port is enabled or disabled in response to the control signal.

Abstract: A graphic accelerator including a frame memory and the same interface as a memory of a processor and a graphic accelerating method are provided. The graphic accelerator includes: a frame memory; an accelerator controller having the same interface as a memory of the processor on an input side and recording data, which should be transmitted from the processor to the display device, in the frame memory; and a display DMA (Direct Memory Access) transmitting the data recorded in the frame memory to the display device in a DMA manner. A memory bandwidth of the processor is not reduced even by continuous reading operations based on DMA transmission of the display device, by recording data corresponding to the frame memory in the graphic accelerator disposed outside the processor.

Abstract: A memory utilizes a data refresh algorithm to preserve data integrity over disturbances caused by memory programming or erase operations. The memory device maintains a counter for each memory block or sector. When a memory block or sector is erased or programmed, the associated counter is set to a first value while other counters are incremented or decremented. Whenever a counter reaches a threshold value, the associated block or sector is refreshed. The threshold value is set to ensure that each block or sector is refreshed before data integrity is adversely affected by disturbances caused by repeated programming and erase operations.

Abstract: A memory system comprises first memory that includes memory cells that are selectively refreshed at a refresh rate. A test module tests operation of the memory cells at the refresh rate and that identifies T of the memory cells that are inoperable when refreshed at the refresh rate, where T is an integer greater than zero. Content addressable memory (CAM) includes D CAM memory cells where D is an integer greater than or equal to one. An adaptive refresh module selectively adjusts a refresh rate of the first memory based on T and D.

Abstract: A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal.

Abstract: The memory system includes a memory cell array including a plurality of memory sectors and a controller configured to write data in the memory cell array in response to a writing signal. The controller is configured to refresh at least one of the plurality memory sectors when the writing signal is provided.

Abstract: This invention improves the access efficiency of each of a plurality of memory devices mounted on a semiconductor chip. The invention provides a memory control circuit including a queue buffer unit, a management unit to set the CKE signal at High for a memory device to which a determination target access command is to be issued when it is determined that the determination target access command has shifted to the head position of the queue buffer unit, a command generating unit to issue an access command, and a data interface unit to execute processing specified by an access command. The management unit performs control to set the CKE signal to Low for the memory device to which the determination target access command is to be issued based on the state of the queue buffer unit when it is determined that the processing by the data interface unit is complete.

Abstract: A refresh method for a semiconductor memory device having more than one bank group is provided. The refresh method may include applying an all-refresh command to one the bank groups, determining if one of the bank groups includes a bank undergoing a refresh operation when the all-refresh command is received, and performing an all-refresh operation based on the determination.

Abstract: To ensure that a memory device operates in self-refresh mode, the memory controller includes (1) a normal-mode output buffer for driving a clock enable signal CKE onto the memory device's CKE input and (2) a power island for driving a clock enable signal CKE_prime onto that same input. To power down the memory controller, the normal-mode output buffer drives signal CKE low, then the power island drives signal CKE_prime low, then the memory controller (except for the power island) is powered down. The power island continues to drive the memory device's CKE input low to ensure that the memory device stays in self-refresh mode while the memory controller is powered substantially off. To resume normal operations, the power module powers up the memory controller, then the normal-mode output buffer drives signal CKE low, then the power island is disabled, then the memory controller resumes normal operations of the memory device.

Abstract: In an LSI that determines timing of DRAM refresh by a refresh timer to synchronize an external I/O signal and DRAM refresh timing with each other, a circuit configuration capable of controlling a value of the refresh timer by a CPU at arbitrary timing is employed. Alternatively, a circuit configuration capable of controlling the value of the refresh timer at arbitrary timing by an external terminal, or a circuit configuration capable of controlling the refresh timing directly from the external terminal without through the refresh timer.

Abstract: In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii) a termination voltage provided by the power module. To power down the memory controller, the memory controller drives the CKE signal low, then the power module drives the termination voltage low, then the power module powers down the memory controller. To resume normal operations, the power module powers up the memory controller, then the memory controller drives the CKE signal low, then the power module powers up the termination voltage. By holding the termination voltage low, the memory circuitry ensures that the memory device stays in self-refresh mode while the memory device is powered down and off.

Abstract: One exemplary memory control method of a memory device includes: determining at least a physical row partition including a plurality of physical rows selected from the memory device; and for each physical row partition, mapping interleaved virtual rows to the selected physical rows. Each physical row partition is a portion of the memory device. Bank addresses of adjacent virtual rows are different. Another exemplary memory control method of a memory device includes: assigning an indicator to each physical row partition in the memory device for indicating if the corresponding physical row partition is to be refreshed; and controlling a partial refresh operation of the memory device according to the indicator of each physical row partition. Each physical row partition is a portion of the memory device.

Abstract: A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The method includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.

Abstract: Systems and methods (“utility”) for providing a computer system with a mechanism to record live data on a continuous basis which may be analyzed subsequent to a fault condition is provided. The utility uses the existing DRAM memory of a computer system as a retentive DRAM (RDRAM) device that may be used to store the data. To accomplish this, software and firmware is provided for continuously refreshing the DRAM memory across resets that are due to fault conditions. Further, non-maskable interrupts (NMI) are used to flag a variety of fault conditions to the computer system. To make the utility platform independent, a standardized power and configuration interface is used to implement a computer system reset that preserves the contents of the RDRAM.

Abstract: Bus transfer efficiency is improved in bus communication that uses a shared memory, based on a communication origin master 101 selectively using an arbitration completion notification signal and a memory access completion notification signal. Based on the arbitration completion notification signal, the communication origin master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing the shared memory 12. Based on the memory access completion notification signal, the communication origin master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing the shared memory 12.

Abstract: A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the time interval between successive memory refresh operations is relatively long, as compared to the time interval between successive memory refresh operations in a conventional volatile memory device, such as a DRAM. A processor can perform periodic memory refresh operations by executing a set of memory refresh instructions implemented in software, rather than in hardware. Accordingly, the memory device can advantageously be simplified, because the need for memory refresh circuitry and for a unique refresh control signal are advantageously eliminated. Moreover, the processor executing the memory refresh instructions can typically perform more sophisticated algorithms, as compared to memory refresh circuitry implemented in hardware, for determining when to perform a memory refresh operation.

Abstract: In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.

Abstract: A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The method includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor.

Abstract: A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.

Abstract: A semiconductor memory device includes a first refresh cycle changing circuit that changes a refresh cycle according to an auto-refresh mode, without giving influence to a refresh cycle according to a self-refresh mode, and a second refresh cycle changing circuit that changes a refresh cycle according to the self-refresh mode, without giving influence to a refresh cycle according to the auto-refresh mode. In this way, according to the present invention, the refresh cycle according to the auto-refresh mode and the refresh cycle according to the self-refresh mode can be controlled independently. Therefore, refresh operation considering the characteristic of each mode can be executed.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.