Abstract: In a system for distributing data, distribution device is configured to distribute timestamp, offset and source location information for a digital data stream to an execution device, and the execution device is configured to seek digital data corresponding to the received information. The execution device is further configured to execute the digital data relative to a clock rate maintained by the distribution device. Related methods include receiving timestamp, offset and source location information for the digital data stream and seeking digital data corresponding to the received offset and source location information.

Abstract: Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input.

Abstract: Adjusting a clock source of a device clock to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The device clock may be derived from an input clock to a serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, it may be determined that the serial interface clock is or will interfere with wireless communication. Accordingly, temporary clock signals may be provided to the device clock while the first clock is modified. Once modified, the modified clock signals may be provided to the device clock to reduce wireless communication interference.

Abstract: In a first embodiment of the present invention, a method for dynamically adjusting a system clock of a plurality of system clock-controlled components in a system is provided, the method comprising: detecting the receipt of a command at a non-system clock-controlled component of the system; and adjusting the system clock to a fast speed based on the detecting. This embodiment may also include: determining that the command has been completed; determining that there are no outstanding commands in the plurality of system clock-controlled components; and adjusting the system clock to a slow speed based on the determination that there are no outstanding commands in the plurality of system clock-controlled components.

Abstract: According to some embodiments, a method and system are provided to initiate communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators, determine a slowest one of the plurality of voltage regulators that is electrically coupled to the integrated circuit, and communicate with the plurality of voltage regulators that are electrically coupled to the integrated circuit at a speed associated with the slowest one of the plurality of voltage regulators.

Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Abstract: According to some embodiments, a method and system are provided to initiate communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators, determine a slowest one of the plurality of voltage regulators that is electrically coupled to the processor, transmit address information to the plurality of voltage regulators that are electrically coupled to the processor at a first speed associated with the slowest one of the plurality of voltage regulators, determine a second speed associated with a voltage regulator to which the address information is associated, and transmit a second portion of the packet at the second speed associated with the voltage regulator to which the address information is associated.

Abstract: A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure (such as a clock carrier signal) containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; and circuitry for receiving the decoded carrier signal, for generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and for passing the software interrupt to the USB microcontroller; wherein the USB microcontroller is configured to respond to the software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal.

Abstract: A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Abstract: A timestamp generator generates a timestamp value having a predetermined number of most significant bits and a predetermined number of least significant bits. The least significant bits are transmitted to a client via a parallel data bus. The most significant bits are transmitted to the client sequentially via a series data bus. Each client receives the parallel least significant bits and the series most significant bits and assembles a complete time stamp value.

Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a third frequency calibration device to share the same oscillator as so to perform multi-stage clock frequency resolution calibrations for different frequency-tuning ranges. This can bring an optimal frequency resolution, greatly reduce system complexity and save element cost.

Abstract: The embodiments disclose a method for encoder frequency-shift compensation, including, determining frequency values of an input encoder signal, analyzing an encoder index clock signal and the input encoder signal to determine values of frequency-shifts and compensating for the values of the frequency-shifts to generate a frequency-shift compensated clock.

Abstract: A device may include a processor to execute a thread. The processor may be further configured to execute a set of wrappers that are called from within the thread to invoke a set of one-shot signal objects to generate delayed signals. Each of the set of wrappers may be configured to detect whether different ones of one-shot signal objects that were invoked from within the thread have generated signals at periodic time intervals, determine a delay to be used for invoking one of the set of one-shot signal objects, and invoke the one of the set of one-shot signal object to generate one of the delayed signals based on the delay when the different ones of one-shot signal objects have generated signals at periodic time intervals. The processor may be further configured to receive the delayed signals generated from the set of one-shot signal objects over a time period.

Abstract: A computer system is provided with an event counter, a CPU, a memory, an external device, a hub M31 and a hub I33. The computer system is further provided with a clock change module 50. System software 60 and applications 70a to 70m operate, and the clock change module 50 specifies a clock with which the applications 70 are executed. Based on stall cycles read from the event counter 21, the clock change module 50 specifies the clock that maximizes performance or power consumption characteristic while satisfying execution constraint 90.

Abstract: An integrated circuit includes physical media attachment (“PMA”) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively usable as phase-locked loop (“PLL”) circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.

Abstract: The present invention extends to methods, systems, and computer program products for using pulses to control work ingress. Generally, embodiments of the invention use a variable-speed clock for accepting work for lower-priority services. A clock rate is controlled by a load monitor. The load monitor periodically collects sensor measurements of resources available after allocations by higher-priority services. Based on the sensor measurements, the load monitor adjusts the clock speed up or down (i.e., depending on the amount of resources available after allocations by higher-priority services). At the boundary of the lower-priority service (e.g., where work enters the system), work requests are enqueued to be associated with a future pulse of the clock. Work is accepted or rejected based on a determination of whether the work request can be allocated a clock pulse within a defined period of time.

Abstract: A method for countervailing clock skew between a first clock signal and a second clock signal in a core logic circuit. The second clock signal is sampled based on the first clock signal in a sampling cycle to obtain a sampling result. When the sampling result indicates a non-compliant pattern, the phase of at least one of the first clock signal and the second clock signal is adjusted. Desirably, the core logic circuit keeps on working with the current first and second clock signals while continuing the sampling procedure of the second clock signal based on the first clock signal when the sampling result indicates a compliant pattern.

Abstract: A computing apparatus and corresponding method for operating are disclosed. The computing apparatus may comprise a set of interconnected central processing units (CPUs). Each CPU may embed an operating system including a kernel comprising a protocol stack. At least one of the CPUs may further embed executable instructions for allocating multiple strands among the rest of the CPUs. The protocol stack may comprise a Transmission Control Protocol/Internet Protocol (TCP/IP), a User Datagram Protocol/Internet Protocol (UDP/IP) stack, an Internet Control Message Protocol (ICMP) stack or any other suitable Internet protocol. The method for operating the computing apparatus may comprise receiving input/output (I/O) requests, generating multiple strands according to the I/O requests, and allocating the multiple strands to one or more CPUs.

Abstract: A computing apparatus and corresponding method for operating are disclosed. The computing apparatus may comprise a set of interconnected central processing units (CPUs). Each CPU may embed an operating system including a kernel comprising a protocol stack. At least one of the CPUs may further embed executable instructions for allocating multiple strands among the rest of the CPUs. The protocol stack may comprise a Transmission Control Protocol/Internet Protocol (TCP/IP), a User Datagram Protocol/Internet Protocol (UDP/IP) stack, an Internet Control Message Protocol (ICMP) stack or any other suitable Internet protocol. The method for operating the computing apparatus may comprise receiving input/output (I/O) requests, generating multiple strands according to the I/O requests, and allocating the multiple strands to one or more CPUs.

Abstract: A multi-core processor and a frequency conversion device thereof as well as a method of communication between the cores are disclosed. Each processor core of the multi-core processor includes a frequency conversion device, which includes a multi-bit state changing means, a multiple selector, a frequency conversion coefficient register, a multi-input OR gate and a clock-gating circuit unit. A common original clock is sent to the frequency conversion device of each processor core at work. The frequency conversion device real-timely reads the value of the frequency conversion coefficient register of a corresponding processor core and receives data transmission valid signals from other processor cores. By gating the common original clock, a frequency conversion function of the processor core is completed.

Abstract: There is described a method for transmitting synchronization messages, for example PTP messages of the IEEE 1588 standard, the PTP message being inserted into a data packet in line with the Internet Protocol, the data packet having an IP header, and the data packet having a UDP header. In this case, for the encrypted transmission on the PTP message, the data packet is addressed to a UDP port that is reserved for encrypted PTP messages, the data packet is provided with an additional S-PTP header that is provided for encryption, the PTP message is extended with a pseudo random number, and the PTP message is encrypted together with the pseudo random number.

Abstract: The claimed subject matter can provide an architecture that interfaces a single slave device such as a UICC smartcard with multiple host controllers. For example, a secondary host can be interfaced between a primary host (e.g., a controller in a cellular phone, a PDA, an MP3 player . . . ) to manage all transactions with the slave device. The secondary host can operate transparently to the primary host and thus does not require any modifications to the primary host. This can be accomplished, e.g., by employing the CMD channel (which is relatively sparsely used by the primary host) to communicate both commands and data with the slave.

Abstract: An apparatus and method for fault-tolerant and spread spectrum clocking. In one embodiment a master clock synthesizer circuit generates an output clock signal of varying frequency within a predetermined range of frequencies. A slave clock synthesizer circuit is provided to track the output clock signal generated by the master clock synthesizer circuit. If the master clock synthesizer circuit fails or generates an invalid output clock signal, the slave clock synthesizer circuit takes over and functions as the master clock synthesizer circuit. In one embodiment a method of fault-tolerant spread spectrum clocking includes generating a first digital data stream; receiving the first digital data stream, a first input reference signal and a first clock signal in a master clock synthesizer circuit; generating an first output clock signal of varying frequency by the master clock synthesizer circuit in response to the first digital data stream and the first clock signal.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit that includes both a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information for an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Abstract: Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.

Abstract: Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock switching in a clock selector operable to switch between clock signals including a first clock signal based on first and second clock-stop-permission signals and a clock-resume-permission signal. The clock-control-signal-generation circuit includes: a before-switching clock processing unit; and an after-switching clock processing unit. In each of the before-and after-switching clock processing units, the high-frequency clock processing subunit and the low-frequency clock processing subunit take partial charges of processing of clock signals involved in the switching respectively, whereby the processing is speeded up.

Abstract: A memory controller takes in the first to (N?1)th pieces of data respectively in synchronization with the second to Nth return read clocks. The memory controller takes in the Nth piece of data from stop of output of the Nth read clock and before a first predetermined time. The memory controller sets an output period of the Nth read clock to be longer than an output period of each of the first to (N?1)th read clocks.

Abstract: Example embodiments disclosed herein relate to storing event data and a time value in memory with an event logging module. Example embodiments of the event logging module include event command storage, clock command storage, and memory command storage.

Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Abstract: Synchronizing a data stream with an associated metadata stream by receiving a data stream and a metadata stream having a plurality of metadata events associated with the data stream, identifying within the data stream a plurality of data events, matching each of the data events to one of the metadata events in accordance with a matching criterion, and synchronizing the data stream with the metadata stream by effecting a relative time shift between the metadata stream and the data stream in accordance with a time shift adjustment value that results in the smallest sum of absolute differences between time indices of each matched data event and metadata event.

Abstract: A device and method for reducing the power consumption of an electronic device using register file with bypass mechanism. The width of a pulse controlling the word write operation may be extended twice as long so that the extended portion substantially overlaps a following word read pulse. The extension of the pulse width of the read operation may enable lowering the Vcc Min value for the electronic device and thus may lower the power consumption of the device.

Abstract: An asynchronous interface circuit for transferring a data stream between different clock domains, the asynchronous interface circuits includes a data holding circuit for sequentially receiving and transferring data of the data stream in synchronism with a first clock signal, and holding the received data until an input of a next data, an asynchronous memory for sequentially receiving the data held in the data holding circuit in synchronism with the first clock signal and for outputting the data in the order of inputting in synchronism with a second clock signal. The asynchronous interface circuit further includes a monitor for detecting an operating state of the asynchronous memory, and a selector for selecting one of the data output from the asynchronous memory and the data output from the data holding circuit on the basis of a detecting result of the monitor.

Abstract: A memory device that has two operating modes. In the first mode the data strobe is source synchronous and is driven by the memory device when data is being transmitted. In the second mode the data strobe is not driven by the memory device. In this mode the data strobe signal is used as a free running clock to sample write data. The capture of read data by the controller is timed by a controller with a calibrated internal timing reference from the system clock.

Abstract: The inter-clock domain data transfer FIFO circuit provides a circuit that transfers data between two clock domains of unrelated frequencies. The gate count is kept relatively low, thereby allowing data transfer between the two clock domains at one data item per cycle of the lower of the two frequencies. Depending on the frequency difference between the data producer and consumer, the initial latency could be as low as a fraction of a cycle and no more than two cycles of the consumer's clock. The operation of the data transfer FIFO circuit has been verified using gate-level simulations for several ratios of clock frequencies.

Abstract: Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal.

Abstract: A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module.

Abstract: A storage device includes a nonvolatile storage section; and a control section that controls the nonvolatile storage section, wherein the control section includes an access control section that outputs a clock for access control for performing access control of a read/write of the nonvolatile storage section, and performs access control of the read/write to the nonvolatile storage section, and a masking process section that performs the masking process of a reset signal on the basis of the clock for access control from the access control section, and supplies the reset signal after the masking process to the access control section.

Abstract: A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock signal to one or more reference time periods to determine the cable plug status.

Abstract: The invention provides an adjusting method of a system for changing a working frequency in an operation system for a computer system. The adjusting method includes establishing a look-up table, and detecting a newest value of the working frequency. An adjustment value can be obtained from the look-up table according to the newest value of the working frequency. In addition, a phase difference of a control signal of a memory is adjusted in the computer system according to the adjustment value and the working frequency is executed stably in optimum status according to the present invention.

Abstract: To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.

Abstract: A transmission apparatus that transmits data according to a protocol has a timer, a memory, a processor, and a transmission unit. The processor stores, in the memory, type data indicating a single type of time from a plurality of types of time that are to be measured according to the protocol. The transmission unit transmits data according to the protocol and starts the measurement of time of the type indicated by the type data stored in the memory using the timer after the data has been transmitted.

Abstract: Systems, methods, and other embodiments associated with clock generation are provided. In one embodiment, a precise timing protocol message is parsed to extract timing information. Timing waveform parameters are calculated based on the timing information and a digital clock is generated based on the waveform parameters. A video stream can then be decoded and rendered, where the rendering depends on the digital clock.

Abstract: Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples.

Abstract: A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.

Abstract: Addressing method for multiple chips is provided. Each chip includes an input enable terminal, an output enable terminal, a data input terminal, and a clock terminal. The output enable terminal of a previous stage is connected to the input enable terminal of a next stage. The method includes setting an initial address to an address of each chip via a system; setting a state of each chip to a disable state; enabling the state of a first-one chip among the chips to an enable state, and setting the first chip as a previous-stage chip; updating the address of the previous-stage chip; enabling a next-stage chip connected after the previous-stage chip, in which the system controls the output enable terminal of the previous-stage chip to output an enable signal to enable the next-stage chip, according to the address of the previous-stage chip; and the updating the address of the next-stage chip.

Abstract: An interface control device includes a first interface, a second interface, a third interface, an interface controller and a clock supplying unit. The first interface is used to communicate with a first information processing device and obtain a first clock signal from the first information processing device. The second interface is used to communicate using a second clock signal with a second information processing device different from the first information processing device. The third interface is used to communicate with a controller of a data-storage medium. The interface controller performs an interface control for the first, second and third interfaces. Moreover, the clock supplying unit supplies the first clock signal to the third interface while communications through the second interface have not been established.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

Abstract: An integrated circuit includes first, second and third circuits, a clock module and a rate adapting module. The first circuit causes frequency dependent noise and is clocked based on a clock signal. The second circuit is rate dependent and is clocked based on an operation dependent clock signal. The third circuit is susceptible to adverse performance when the frequency dependent noise has a component within a given frequency range. The clock module generates a clock signal having a rate such that frequency dependent noise components associated with the clock signal are outside the given frequency range. The rate adapting module is coupled to produce the operation dependent clock signal from the clock signal.