Abstract: A device and method of making a device is disclosed. One embodiment provides a substrate. A semiconductor chip is provided having a first surface with a roughness of at least 100 nm. A diffusion soldering process is performed to join the first surface of the semiconductor chip to the substrate.

Abstract: Systems and methods of removing bacterial biofilm from a target site using a biofilm removal endoscope. The endoscope has an insertion portion including an imaging channel terminating at a viewing window and an irrigation channel terminating at a nozzle. The imaging and irrigation channels are permanently affixed relative to one another. The insertion portion is inserted into the patient, with a working end thereof being disposed proximate the target site. The target site is imaged and a flow of fluid is dispensed via the nozzle to mechanically remove bacterial biofilm from the target site.

Abstract: A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip.

Abstract: An integrated circuit includes a first bit line and a resistance changing memory element coupled to the first bit line. The integrated circuit includes a second bit line and a heater coupled to the second bit line. The integrated circuit includes an access device coupled to the resistance changing memory element and the heater.

Abstract: A tester includes a device under test (DUT) power supply (DPS) with and input and output includes an amplifier configured to set an output voltage of the DPS output equal to an input voltage for the DPS. The DPS has a first output stage coupled to the amplifier and configured to source and sink current at the output of the DPS between a first voltage rail and a third voltage rail. The DPS has a second output stage coupled to the amplifier and configured to source and sink current to the output of the DPS between a second voltage rail and the third voltage rail. A selection device is configured to enable the first and second output stages based on a selection input signal. The selection device is situated outside of the first and the second output stages.

Abstract: A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallization region is formed on the machined second surface of the semiconductor wafer.

Abstract: A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least one semiconductor chip and on the at least one element.

Abstract: A pipe gripper device including first and second gripper bodies and a clevis assembly. The gripper bodies each have a head and an arm. The head forms a slot. The arm defines a grip segment proximate a leading end and forms a textured exterior surface. The arms are pivotably coupled and slidably contact one another along corresponding interiors. The clevis assembly includes a clevis mounted to the heads by a pin passing through the respective slots. The gripper device is transitionable between a contracted state and an expanded state by pivoting of the gripper bodies at the corresponding pivot points, with the pin sliding within the slots to define a limit of the expanded state. In the contracted state, the grip segments are readily inserted into a pipe; upon transitioning toward the expanded state, the grip segments engage the pipe interior for application of a pulling force.

Abstract: A semiconductor device having a semiconductor body, a source metallization arranged on a first surface of the semiconductor body and a trench including a first trench portion and a second trench portion and extending from the first surface into the semiconductor body is provided. The semiconductor body further includes a pn-junction formed between a first semiconductor region and a second semiconductor region. The first trench portion includes an insulated gate electrode which is connected to the source metallization, and the second trench portion includes a conductive plug which is connected to the source metallization and to the second semiconductor region.

Abstract: A system including a first circuit, a second circuit, and a feedback circuit. The first circuit is configured to provide input signals. The second circuit is configured to receive the input signals and provide digital output signals that correspond to the input signals. The feedback circuit includes a chopping circuit, an integrator circuit, and a digital to analog converter circuit. The chopping circuit is configured to receive the digital output signals and provide error signals that represent ripple error in the digital output signals. The integrator circuit is configured to accumulate the error signals and provide an accumulated error signal. The digital to analog converter circuit is configured to convert the accumulated error signal into an analog signal that is received by the second circuit to reduce the ripple error.

Abstract: Methods and apparatus for placing wafers axially in an optical inspection system. A “best worst” focus method includes a series of through-focus images of a test wafer acquired using full field of view of the inspection optics. The value of the worst quality in each image is associated with the respective axial location, forming a locus of “worst” values as a function of axial location. The axial location is chosen which optimizes the locus, giving an axial location that provides the “best-worst” image quality. A “video focus” method includes a series of through-focus images generated using reduced field of view. A figure of merit is associated with each image, providing through-focus information. The “video focus” can be calibrated against the “best worst” focus. Further, a point sensor can be used to generate a single z-value for one (x,y) location that can be calibrated with “video focus”.

Abstract: One aspect is a method of manufacturing a semiconductor device and semiconductor device. One embodiment provides a plurality of modules. Each of the modules includes a carrier and at least one semiconductor chip attached to the carrier. A dielectric layer is applied to the modules to form a workpiece. The dielectric layer is structured to open at least one of the semiconductor chips. The workpiece is singulated to obtain a plurality of devices.

Abstract: A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.

Abstract: A semiconductor substrate and a method for producing it is disclosed. In one embodiment, a contact region and a corresponding contact material of the semiconductor substrate are formed, in regions or completely, with a protection against oxidation.

Abstract: A portable truck dump comprises a conveyor system mounted on an elongate frame to transport material from a first end of the frame to a second, opposite end of the frame. A grate is positioned over the conveyor system and is supported by first and second sides of the frame. A ramp extends generally perpendicular to the frame on each side of the frame next to the grate to provide a drive-over access for a material transport vehicle to deposit its load over the grate and onto the conveyor system and a portion of each ramp. A first end of each ramp immediately adjacent to the frame is pivotally connected to the frame to allow the ramp to be articulated towards the grate to move excess material off of the ramp and into the grate.

Abstract: One embodiment provides a semiconductor wafer structure including a semiconductor wafer and a spacer layer. The semiconductor wafer includes active areas. The spacer layer is configured to provide spacing between the semiconductor dice in a stacked die package and the spacer layer is disposed on one side of the semiconductor wafer.

Abstract: By examining scrub mark properties (such as position and size) directly, the performance of a wafer probing process may be evaluated. Scrub mark images are captured, image data measured, and detailed information about the process is extracted through analysis. The information may then be used to troubleshoot, improve, and monitor the probing process.

Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.

Abstract: A semiconductor component including a drift zone and a drift control zone. One embodiment provides a transistor component having a drift zone, a body zone, a source zone and a drain zone. The drift zone is arranged between the body zone and the drain zone. The body zone is arranged between the source zone and the drift zone.

Abstract: An integrated circuit device includes a semiconductor chip with a metallization layer on the chip. A gas-phase deposited insulation layer is disposed on the metallization layer.