Abstract: An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.

Abstract: An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a heat sink plate and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the heat sink plate. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

Abstract: A semiconductor and method for manufacturing a semiconductor device. In one embodiment the method includes providing a semiconductor substrate with a first substrate surface and at least one trench having at least one trench surface. The trench extends from the first substrate surface into the semiconductor substrate. The trench has a first trench section and a second trench section. The trench surface is exposed in an upper portion of the first and second trench sections and covered with a first insulating layer in a lower portion. A second insulating layer is formed at least on the exposed trench surface in the upper portion. A conductive layer is formed on the second insulating layer at least in the upper portion, wherein the second insulating layer electrically insulates the conductive layer from the semiconductor substrate. The conductive layer is removed in the first trench section without removing the conductive layer in the second trench section.

Abstract: A multi-chip module is disclosed. In one embodiment, the multichip module includes a first chip, a second chip and a common chip carrier is disclosed. The first chip and the second chip are mounted on the common chip carrier. The second chip is mounted on the chip carrier in a flip-chip orientation. The second chip is electrically connected to the first chip via the chip carrier.

Abstract: A mold assembly for use with an automated dry cast concrete machine including a plurality of mold cavities, each mold cavity formed by a plurality of liner plates, wherein at least one liner plate of each mold cavity is moveable between an extended position and a retracted position relative to an interior of the mold cavity. The mold assembly further includes a master bar in mechanical communication with the at least one moveable liner plate of each of the mold cavities, and an actuator configured to drive the master bar in a first direction and a second direction, which is opposite the first direction, to respectively direct movement of the at least one moveable liner plate of each of the mold cavities between the extended and retracted positions.

Abstract: An integrated circuit includes a first electrode including an etched recessed portion. The integrated circuit includes a second electrode and a resistivity changing material filling the recessed portion and coupled to the second electrode.

Abstract: A position identification system and method include a receiver configured to receive an initiation signal and attenuate the initiation signal until the initiation signal is within a first predetermined range of a reference signal. A controller identifies the position of the receiver in response to the attenuation.

Abstract: The invention relates to a memory device, in particular to a resistively switching memory device such as a Phase Change Random Access Memory (“PCRAM”). In one disclosed method, a nanowire of non-conducting material is formed serving as a mould for producing a nanotube of conducting material. A volume of switching active material is deposited on top of the nanotube, so that the ring-shaped front face of the nanotube couples to the switching active material and thus forms a bottom electrode contact.

Abstract: One aspect includes a semiconductor device with self-aligned contacts, integrated circuit and manufacturing method. One embodiment provides gate control structures. Each of the gate control structures is configured to control the conductivity of a channel region within a silicon carbide substrate by field effect. A contact hole is self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers.

Abstract: A method for evaluating a performance of a substrate surface including applying a normal force with a probe to a surface of a substrate, the normal force being substantially perpendicular to the surface, and moving the probe across the surface to generate a force against and to scratch the surface, the force being substantially parallel to the surface and comprising a coaxial force along the scratch and an orthogonal force perpendicular to the scratch. The method further includes measuring a magnitude of the orthogonal force as the probe moves across the coating, and determining a fracture point of the surface by the probe based on changes in the magnitude of the orthogonal force.

Abstract: A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high resistivity region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high resistivity region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided.

Abstract: A system including a receiver and a transmitter. The receiver is configured to transmit a request. The transmitter is configured to transmit a reply signal that at least partially overlaps the request.

Abstract: A semiconductor device test system has an interface for use with a semiconductor device test method, and a semiconductor device test method. In a first mode of an interface, in reaction to test signals corresponding to a test standard, for example, a JTAG test standard, and received by the interface from a test device, the interface outputs signals corresponding to the test standard to a semiconductor device to be tested. In a second mode of the interface, in reaction to test signals corresponding to the test standard and received by the interface from a test device, the interface outputs signals that do not correspond to the test standard to a semiconductor device to be tested.

Abstract: A semiconductor device includes first semiconductor zones of a first conductivity type having a first dopant species of the first conductivity type and a second dopant species of a second conductivity type different from the first conductivity type. The semiconductor device also includes second semiconductor zones of the second conductivity type including the second dopant species. The first and second semiconductor zones are alternately arranged in contact with each other along a lateral direction extending in parallel to a surface of a semiconductor body. One of the first and second semiconductor zones constitute drift zones and a diffusion coefficient of the second dopant species is at least twice as large as the diffusion coefficient of the first dopant species. A concentration profile of the first dopant species along a vertical direction perpendicular to the surface of the semiconductor body includes at least two maxima.

Abstract: A system includes a first circuit configured to convert a first analog signal to a first digital signal. The system includes a second circuit configured to determine an area of the first digital signal above a set value and an area of the first digital signal below the set value to provide a second digital signal indicating an offset of the first analog signal.

Abstract: A memory circuit includes multiple memory chips configured to store data and disposed in at least one stack. The memory circuit includes multiple ports configured to receive and transmit control signals and data to and from the memory chips and to supply energy to the memory circuit. The memory circuit includes a housing accommodating the multiple memory chips and the multiple ports.

Abstract: A device including a semiconductor chip. One embodiment provides a device, including a metal layer having a first layer face. A semiconductor chip includes a first chip face. The semiconductor chip is electrically coupled to and placed over the metal layer with the first chip face facing the first layer face. An encapsulation material covers the first layer face and the semiconductor chip. At least one through-hole extends from the first layer face through the encapsulation material. The at least one through-hole is accessible from outside the device.

Abstract: A semiconductor component is disclosed. In one embodiment, the semiconductor component includes a semiconductor chip, which is arranged on a substrate, and a housing, which at least partially surrounds the semiconductor chip. The substrate is at least partly provided with a layer of polymer foam.

Abstract: A bonding material including a meltable joining material and a plurality of heterostructures distributed throughout the meltable joining material, the heterostructures comprising at least a first material and a second material capable of conducting a self-sustaining exothermic reaction upon initiation by an external energy to generate heat sufficient to melt the meltable joining material.

Abstract: Some aspects of the present invention relate to a wafer inspection method. A plurality of images is acquired about an edge portion of a wafer. Each of the images comprises a pixel array having a first dimension and a second dimension. A composite image of compressed pixel arrays is generated by compressing each of the pixel arrays in the first dimension and concatenating the pixel arrays. The composite image is analyzed to identify a wafer feature, for example using a sinusoidal line fit.