Patents Represented by Attorney Hayes Soloway P.C.
  • Patent number: 6995367
    Abstract: A near-field light detecting apparatus providing a high spatial resolution comprises a near-field light sensor for converting near-field light from the surface of a sample into an electric signal, and a voltage source for applying a predetermined voltage to the near-field light sensor through wires. The near-field light sensor comprises a nanotube which has an insulating property in a predetermined area. Electronic excitation is induced by the near-field light in two areas separated by the insulating area to convert the near-field light into the electric signal.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: February 7, 2006
    Assignee: NEC Corporation
    Inventor: Yoshiyuki Miyamoto
  • Patent number: 6991965
    Abstract: In a production method for manufacturing a plurality of chip-size packages, a plurality of semiconductor chip areas are defined on a surface of a wafer, each of the chip areas being produced as a semiconductor device having a plurality of electrode pads formed thereon. A plurality of sprout-shaped metal bumps formed on each device such that the respective metal bumps are bonded on the pads formed on a corresponding semiconductor device. A resin-sealing layer is formed on the surface of the wafer such that tips of the metal bumps formed on each of the devices are projected from a top surface of the resin-sealing layer. A plurality of wiring patterns are formed on the top surface of the resin-sealing layer such that each of the wiring patterns is allocated to a corresponding semiconductor device, and such that electrical connections are established between each of the wiring patterns and the tips of the metal bumps formed on the corresponding semiconductor device.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: January 31, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Yoshihiro Ono
  • Patent number: 6992522
    Abstract: In a negative voltage boosting circuit in which a plurality of boosting unit circuits for boosting negative voltage are connected in series between the input and output terminals of the negative boosting circuit for generating negative voltage at the output terminal. Each of such circuits includes a MOS transistor for transferring charge having one of either the source or the drain connected to an input terminal of the boosting circuit and the other of the source or the drain connected to an output terminal of the boosting circuit. At least one MOS transistor has a well region forming a channel region of the MOS transistor for transferring charge. The well region is biased by electric potential at the output terminal of another boosting unit circuit in an output direction from the biased boosting unit circuit.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: January 31, 2006
    Assignee: Nec Electronics Corporation
    Inventor: Masamichi Ido
  • Patent number: 6992050
    Abstract: A stripping composition comprising (a) an anticorrosive agent, (b) a stripping agent and (c) a solvent, wherein the anticorrosive agent (a) is a heterocyclic compound having a nitrogen atom-containing six-membered ring.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: January 31, 2006
    Assignee: NEC Corporation
    Inventors: Tatsuya Koita, Keiji Hirano, Hidemitsu Aoki, Hiroaki Tomimori
  • Patent number: 6993507
    Abstract: A bill payment system consistent with the invention comprises a biller generating at least one invoice for at least one customer, the invoice comprising a unique bar code comprising data identifying at least the customer and the biller, and a scanning apparatus configured to scan the bar code and, based on the identifying data of the bar code, to effect payment to the biller in a predetermined amount. In method form, a bill payment method consistent with the invention comprises: generating an invoice for at least one customer, said invoice comprising a unique bar code, said bar code comprising data identifying at least said customer and said biller; and permitting a third party to scan said bar code and, based on the identifying data of said bar code, to effect payment to said biller in a predetermined amount.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: January 31, 2006
    Assignee: Pacific Payment Systems, Inc.
    Inventors: John Meyer, Lou Krouse
  • Patent number: 6990031
    Abstract: In a semiconductor memory device which requires a refresh operation, a control method stops supplying a word line voltage which is a boosted voltage higher than an external supply voltage, a memory array substrate voltage which is a negative voltage supplied to a semiconductor substrate, and a bit line precharge voltage for use in reproducing data held in memory cells for a predetermined period at the end of each refresh operation. In this event, voltage output terminals of the word line and memory array substrate voltages are respectively driven to a ground potential. For recovering these voltages, the delivery of the word line voltage is stopped until the memory array substrate voltage rises to some extent.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: January 24, 2006
    Assignee: Elpida Memory, Inc.
    Inventors: Takeshi Hashimoto, Yutaka Ito
  • Patent number: 6980119
    Abstract: The present invention relates generally to warning lights, and more specifically, to solid-state (LED) warning light whose operation is modulated in response to environmental conditions, generally under the supervision of a microprocessor or dedicated control circuit. LEDs are used in warning lights, but not in an effective way. Typically, the LED driving circuits are electrically inefficient and in some cases, there is an attempt to minimize the power that is supplied to the LEDs. The invention employs environmental sensors which allow the operation of the LEDs to be optimized; for example: LED intensity can be increased in response to poor ambient visibility, duty cycle can be decreased in response to a lack of power, and the LEDs can be de-rated in response to high temperature conditions. Many other advantages of the invention are described, including the use of light control film, buck boost and buck down driver circuits, external communication circuits and microprocessor control.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: December 27, 2005
    Assignee: SWS Star Warning Systems Inc.
    Inventors: John W. Toulmin, Francis Balogh
  • Patent number: 6979845
    Abstract: A semiconductor device includes a semiconductor region of a first conductive type. First and second regions of a second conductive type opposite to the first conductive type are provided in a surface of the semiconductor region in a predetermined interval. A third region of the first conductive type is provided between the first and second regions in the surface of the semiconductor region. A fourth region of the first conductive type is provided below the third region inside the semiconductor region to cover the whole of bottom of the third region at least.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: December 27, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Hiroshi Kawaguchi, Riki Mizuno
  • Patent number: 6974759
    Abstract: The invention relates to a process for manufacturing a stacked structure comprising at least one thin layer bonding to a target substrate, comprising the following steps: a) formation of a thin layer starting from an initial substrate, the thin layer having a free face called the first contact face, b) putting the first contact face into bonding contact with a face of an intermediate support, the structure obtained being compatible with later thinning of the initial substrate, c) thinning of the said initial substrate to expose a free face of the thin layer called the second contact face and opposite the first contact face, d) puffing a face of the target substrate into bonding contact with at least part of the second contact face, the structure obtained being compatible with later removal of all or some of the intermediate support, e) removal of at least part of the intermediate support in order to obtain the said stacked structure.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: December 13, 2005
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Bernard Aspar, Eric Jalaguier, Fabrice Letertre
  • Patent number: 6973115
    Abstract: This invention relates to a laser cavity with passive triggering by saturable absorbent and with controlled polarization, and to a laser and in particular to a microlaser containing the said cavity and means of pumping this cavity. The invention also relates to a process for manufacturing the said microlaser. The laser cavity with controlled polarization comprises a substrate made of Y3Al5O12 (YAG) active laser material that may or may not be doped, on which a monocrystalline layer of saturable absorbent doped YAG material is deposited directly by liquid phase epitaxy or by a similar process, in which the said active laser material has a [100] orientation, and in which the said monocrystalline layer of saturable absorbent material is deposited with the same [100] orientation.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: December 6, 2005
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Bernard Ferrand, Bernard Chambaz, Laurent Fulbert, Jean Marty
  • Patent number: 6972488
    Abstract: A semiconductor device includes (a) a printed wiring board, (b) a semiconductor chip mounted on the printed wiring board, (c) a molded resin formed on the printed wiring board, covering the semiconductor chip therewith, and (d) at least one metal wiring formed on the printed wiring board and extending externally beyond the molded resin. The metal wiring is plated with a metal having a small adhesion force with the molded resin. An interfacial surface between the metal and the molded resin acts as a path through which moisture contained in the semiconductor device escapes outside when the semiconductor device is heated.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: December 6, 2005
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Taibo Nakazawa, Hiroyuki Kimura
  • Patent number: 6972821
    Abstract: An active-matrix addressing LCD device that suppresses effectively the off leakage current induced by the charge-up of the spacers placed over the TFTs. The device comprises (a) a first substrate having switching elements; (b) a second substrate coupled with the first substrate in such a way as to form a gap with spacers between the first and second substrates; the spacers being distributed in the gap; (c) a liquid crystal confined in the gap; and (d) protrusions formed in overlapping areas with the switching elements; each of the protrusions being protruded in a direction that narrows the gap. The spacers distributed in the gap are likely to be shifted away from the overlapping areas due to the protrusions.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: December 6, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Kyounei Yasuda, Satoshi Ihida
  • Patent number: 6969283
    Abstract: In order to fix a connector contact insert that is provided with sheet metal flanges in a connector housing that is composed of two interconnectable rectangular shells, the invention proposes a mounting device that is respectively arranged in the corner regions of the shells. The device respectively comprises two integral elements that are spaced apart from one another and form a receptacle slot, wherein differently shaped spring elements can, depending on the respective application, be pushed onto said integral elements or fixed on the shell housing. When assembling the connector, the sheet metal flanges are inserted into the receptacle slots and the two shells are interconnected, wherein the spring elements ensure a shakeproof mounting of the connector contact insert in the connector housing.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: November 29, 2005
    Assignee: Harting Electric GmbH & Co. KG
    Inventor: Martin Schmidt
  • Patent number: 6970369
    Abstract: In a memory device having a controller and multiple memory modules both of which are mounted together on a motherboard, a high-speed operation is executed by suppressing waveform distortion caused by signal reflection. Since signal reflection occurs when a controller performs the writing/reading of data relative to memory units on memory modules, active terminator units are included in the controller and the memory units. These active terminator units are provided for a data bus and/or a clock bus in order to terminate these buses in memory units. The active terminator units provided for the controller and the memory units may be put into an inactive state when data is to be received.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: November 29, 2005
    Assignee: Elpida Memory, Inc.
    Inventors: Seiji Funaba, Yoji Nishio
  • Patent number: 6965531
    Abstract: An open-bit semiconductor memory device includes a plurality of memory cell arrays, wherein half of the memory cells in the memory cell array and half of the memory cells in the adjacent memory cell array store therein complementary data. The memory device further includes a pair of reference cell arrays sandwiching therebetween the memory cell arrays for supplying reference data for reading data from the memory cells in the adjacent memory cells. The reference cell array includes a plurality reference bit lines each connected to reference cells in number smaller than the number of memory cells connected to the bit line, and yet has a resistance and a capacitance equivalent to the resistance and the capacitance of the bit lines.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: November 15, 2005
    Assignee: Elpida Memory, Inc.
    Inventor: Koji Mine
  • Patent number: 6964324
    Abstract: A damper in which magnetic particles are discouraged from settling irrespective of the kind of a magnetic fluid is provided. A damper is constituted of a vessel in which the magnetic fluid is accommodated and a slider (piston). As the piston, one that is made of a laminated body of a paramagnetic substance and a non-magnetic substance is used. When thus constituted, the magnetic particles stick to the piston. Accordingly, whatever magnetic fluid is used, the particles do not settle. The laminated body that is used as the piston has the non-magnetic substance at both ends thereof. When the laminated body is thus constituted, the magnetic particles sticks uniformly. When the laminated body has the magnetic substance at both ends, magnetic particles stick to both ends needle-like.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: November 15, 2005
    Assignee: Tohoku Techno Arch Co., Ltd.
    Inventors: Kunio Shimada, Hideto Kanno
  • Patent number: 6965259
    Abstract: A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: November 15, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Takanori Saeki
  • Patent number: 6964703
    Abstract: Novel starch-based glue paste compositions are disclosed composed of (i) a carrier paste containing 5 to 16 wt % of a starch selected from the group consisting of corn starch, wheat starch, rye starch, oat starch, barley starch, potato starch, tapioca starch and pea starch, each being native starch or chemically modified starch, or any mixture thereof and (ii) a main paste with a total starch content of 25 to 50 wt % composed of a mixture of 10 to 30 wt % native rice starch or an acetylated version thereof having an amylose content of 12 to 20 wt %, 1 wt % other compounds and a complementary amylopectin content of 87 to 79 wt %, and 90 to 70 wt % of a starch or mixture of starches selected from the above defined group. Processes for the manufacture of the novel glue paste compositions based on the Stein-Hall method are disclosed, as well as a premix of starches for said manufacture.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: November 15, 2005
    Assignee: Remy Industries N.V.
    Inventor: Johan Geeroms
  • Patent number: 6962231
    Abstract: A steering handle of a pallet truck is arranged over a battery box on the truck. The steering handle is journaled so that it is in a turnable relation to an arm about a journaling point. The arm is journaled so that it is pivotable around a second pivot point. By pivoting the arm laterally a position may be achieved where the handle is easily accessible from the side of the truck. The steering handle is pivotably arranged in the outer end of the arm in a pivot bearing that in turn is pivotable in the arm and parallel controlled in relation to the truck. Between the steering handle and the journal for the pivot movement detection means are arranged to detect the mutual turning that is then used to electronically/electrically turn the steered wheel of the truck.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: November 8, 2005
    Assignee: BT Industries AB
    Inventors: Magnus Carlsson, Gert Précenth, Sven-Eric Wernborg
  • Patent number: D511245
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: November 8, 2005
    Assignee: Lisa Frank, Inc.
    Inventor: Lisa Frank Green