Patents Represented by Attorney Hayes Soloway P.C.
  • Patent number: 6959422
    Abstract: A shortcut key manager and method is provided for managing shortcut key assignment to non-command user interface items. In response to receipt of an item identification that identifies a non-command user interface item type and a key identification that identifies a shortcut key, the shortcut key is assigned to the non-command user interface item type that defines the non-command item. When the shortcut key is input, an instance of the non-command user interface item is presented to the user in response to the user input of the shortcut key.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: October 25, 2005
    Assignee: Corel Corporation
    Inventors: Don Slaunwhite, Stephen Mereu
  • Patent number: 6958532
    Abstract: A semiconductor storage device enables various plural memories to be mounted on the same package, and even though size of respective chips and/or position of bonding pad are different, it is capable of providing a stack MCP in which the chips are superimposed. It causes wiring sheet to intervene between an upper chip and a lower chip. There are provided bonding pads and a wiring pattern for connecting these bonding pads in the wiring sheet. A bonding pad of the upper chip is connected to the bonding pad by a first bonding wire, while the bonding pad is connected to a bonding pad of the package substrate by a second bonding wire. According to this construction, the signal from the upper chip is transmitted to the package substrate via the wiring sheet.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: October 25, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Sadao Nakayama
  • Patent number: 6955557
    Abstract: A connector with insulation displacement contacts for connecting electric conductors, in which the insulation displacement contacts are held in a carrier body and the electric conductors are guided in conductor guide channels of a conductor guide component. When the carrier body and conductor guide component are joined together the electric conductors are contacted by the insulation displacement contacts. The carrier body and conductor guide component are joined by means of an assembly tool constructed as a half-shell housing, in which bevels are provided which cooperate with bevels on the conductor guide component, so when the carrier body and the conductor guide component are pressed together in the half-shell housing, the carrier body and conductor guide component are pressed together by mutual displacement on the bevels.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: October 18, 2005
    Assignee: Harting Electronics GmbH & Co. KG
    Inventors: Jean Francois Bernat, Jean-Merri de Vanssay, Abdallah Fakhri, Andreas Huhmann, Simon Seereiner
  • Patent number: 6956167
    Abstract: A lid-member holder is used to define envelopers encapsulating electronic components in production of hollow-package type electronic products. A plurality of lid members are temporarily held by the holder body. The lid members are arranged so as to be consistent with an arrangement of surrounding wall members, which are to be sealed with the lid members in a lump to define the envelopers, and the temporary holding of the lid members by the holder body is realized such that lid members can be separated from the lid members after the surrounding wall members are completely sealed with the lid members, without the lid members being removed from the surrounding wall members.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: October 18, 2005
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Toshimichi Kurihara, Takashi Ueda
  • Patent number: 6951512
    Abstract: There is provided an apparatus for polishing a substrate, including (a) a polishing pad formed with a plurality of through-holes through which polishing material is supplied to a surface of the polishing pad, (b) a level block on which the polishing pad is mounted, and (c) a rotatable carrier for supporting a substrate thereon, the carrier being positioned in facing relation with the level block, the level block being rotatable around a rotation axis thereof with the rotation axis being moved along an arcuate path, and causing the polishing pad to make contact with the substrate for polishing the substrate, the polishing pad having a first ring-shaped region concentric thereto where no through-holes are formed. For instance, the first ring-shaped region has a width greater than 10%, but smaller than 95% of a radius of the polishing pad. The apparatus enhances uniformity in polishing a substrate.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: October 4, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Mieko Suzuki, Yasuaki Tsuchiya
  • Patent number: 6950137
    Abstract: An integrated noise reduction circuit for a charge coupled imaging device having a floating diffusion type amplifier which converts signal electric charges obtained by photoelectric conversion into a voltage signal. The noise reduction circuit has a biasing circuit which is coupled to an input terminal for receiving an output signal of the charge coupled imaging device via a coupling capacitor and which supplies a predetermined bias potential to the first input terminal, a clamping circuit which clamps each of reset potential output portions of a signal that is supplied from the biasing circuit via a clamping capacitor and that has the predetermined bias potential applied by the biasing circuit to a predetermined reference potential, and a sample and hold circuit which samples and holds signal potential output portions of a signal outputted from the clamping circuit by using sampling pulses.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: September 27, 2005
    Assignee: NEC Corporation
    Inventor: Takanori Tanaka
  • Patent number: 6944433
    Abstract: A portable telephone apparatus, includes a body and an antenna section. The antenna section includes an antenna element, and a plurality of reflectors provided near the antenna element. The antenna section is provided at a end side where a microphone is provided of the body.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: September 13, 2005
    Assignee: NEC Corporation
    Inventor: Tooru Ogino
  • Patent number: 6940553
    Abstract: To provide a solid-state image sensor, wherein no field adjustment of timing pulse phases used in the signal processor or of signal balances is needed, and noise performance is more improved, with a simple, miniaturized and economical configuration, a solid-state image sensor (1) of the invention comprises: a CCD (2) configured on a semiconductor chip for generating a CCD signal according to an optical image focused on a sensor area thereof; an on-chip signal processor (4) configured on the semiconductor chip by way of the same fabrication process with the CCD including a noise reduction circuit for eliminating noises from the CCD signal, an AGC circuit for amplifying output of of the noise reduction circuit; and a timing pulse generator (3) configured on the semiconductor chip by way of the same fabrication process with the CCD (2) for generating timing pulses used the on-chip signal processor.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: September 6, 2005
    Assignee: NEC Corporation
    Inventor: Satoshi Katoh
  • Patent number: 6938767
    Abstract: A container for welding wire comprises a box-like body having a bottom and a side wall, the side wall having a polygonal cross section with corners, and stabilizing elements arranged at at least some of the corners. The stabilizing elements extend upwardly from the bottom and have an outer shell portion comprising a corner portion facing the adjacent side wall and an inner portion facing an interior of the container for housing welding wire. The corner portion has a shape adapted to the shape of the adjacent corner. The inner portion defines a continuous inner wall.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: September 6, 2005
    Assignee: Sidergas SpA
    Inventor: Carlo Gelmetti
  • Patent number: 6940796
    Abstract: The optical disk device according to the present invention has a data reader which reads data of an optical disk, the disk being provided in advance with an alternate area that serves as a substitute for a defective data area when there is a defect in a data area. The disk is recorded in advance with list information consisting of a plurality of sets each of the sets comprising a position on the disk for the data area and an address of the alternate area. The optical disk also includes buffers for buffering a data area that is defective after correcting it, and a storage device for storing a new alternate list on which is recorded the correspondence relationship between the alternate area and its buffer destination.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: September 6, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Takeo Ariyama
  • Patent number: 6936188
    Abstract: A zinc oxide semiconductor material comprising at least zinc and oxygen as constituent elements, which can be deterred with respect to the deterioration of doping characteristic, luminous characteristic and the like, compared with a conventional c-axial oriented one by orienting the crystal orientation plane to a-axis of the wurtzite structure.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: August 30, 2005
    Assignees: Tohoku Techno Arch Co., Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Koichi Haga
  • Patent number: 6937485
    Abstract: In a duty ratio detecting apparatus, a duty ratio detecting circuit is constructed by first and second nodes, a load current supplying circuit for supplying first and second load currents to the first and second nodes, respectively, and a current switch connected to the first and second nodes. The current switch is operated in response to first and second complementary duty ratio signals. A duty ratio maintaining circuit is constructed by third and fourth nodes for receiving and maintaining voltages at the first and second nodes, respectively. A first switch is connected between the first and third nodes, and a second switch is connected between the second and fourth nodes. The load current supplying circuit is controlled by voltages at the third and fourth nodes.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: August 30, 2005
    Assignee: Elpida Memory, Inc.
    Inventors: Misao Suzuki, Kazutaka Miyano
  • Patent number: 6937081
    Abstract: A delay adjusting circuit that can minimize a delay at selectors even when the number of delay stages and the number of selector stages are increased, to enable a stable and speedy operation. As selectors S in a delay producing circuit (11), 2:1 selectors, each of the type that selectively outputs one from two inputs, may be used which are connected to input/output portions of N-stage delay elements D1 to DN for enabling delayed output of an even-stage delayed clock signal (Even) and an odd-stage delayed clock signal (Odd). In this case, the 2:1 selectors are arranged in a two-stage configuration including the for-even-stage selectors (S1, S3, . . . , Sn, S(n+2)) and the for-odd-stage selectors (S2, . . . , S(n+1), S(n+3)). The even-stage delayed clock signal (Even) is obtained through the first-stage selector S1. The odd-stage delayed clock signal (Odd) is obtained through the second-stage selector S2.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: August 30, 2005
    Assignee: Elpida Memory, Inc.
    Inventor: Toru Ishikawa
  • Patent number: 6933612
    Abstract: A semiconductor device for an improved heatsink structure. The semiconductor device is composed of a first substrate, a first heatsink plate connected to the first substrate, a second substrate having a rear surfaces connected to the first heatsink plate, a semiconductor chip having a main surface bonded to a main surface of the second substrate, and a second heatsink plate connected to a rear surface of the semiconductor chip.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: August 23, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Naoto Kimura
  • Patent number: 6933750
    Abstract: A buffer circuit includes first and second transistors which are connected in series between first and second power supplies and which are controlled to be on/off based on values of signals at their control terminals are provided, in which a connection point between the two transistors is connected to an output terminal (OUT) and a control terminal of the first transistor is connected to an input terminal (IN), and a control circuit for performing on/off control over the second transistor based on an input signal from the input terminal (IN).
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: August 23, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Hiroyuki Takahashi, Hiroyuki Satake
  • Patent number: 6930036
    Abstract: A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: August 16, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Tatsuya Usami
  • Patent number: 6928765
    Abstract: A rope severing apparatus for releasing a rope after continued tension. The first element of the apparatus is the base, which has elastic properties that permit the base to stretch when realizing tensional forces. The base may be a spring in one embodiment, although those skilled in the art would recognize there are other available elements with similar elastic properties that alternatively may be used. The base is connected to a first connection point wherein the first connection point is formed to admit the rope. Preferably the first connection point is a hole through which the rope can be run and tied off. Finally, the present invention requires a cutting edge connected to the base and slidably oriented with the first connection point. The cutting edge is arranged so that it will slide toward the first connection point and sever the rope when the apparatus realizes a tensional force.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: August 16, 2005
    Assignee: Blue Water Concepts, Inc.
    Inventor: Ben Brickett
  • Patent number: 6928722
    Abstract: A recording/reproduction element is mounted on a magnetic head slider via a piezoelectric element so that a displacement of the piezoelectric element performs fine control of the position of the recording/reproduction, thus enabling fine spacing and high track positioning accuracy. This improves linear recording density and track density. A pair of electrodes are formed on both sides of a piezoelectric element to constitute a piezoelectric actuator. One electrode is arranged opposite the rear surface (air flow out end) of a magnetic head slider 11. A recording/reproduction element is arranged on and electrically insulated from the other electrode. The piezoelectric element includes a piezoelectric element displaced in a spacing direction, enabling fine spacing control, a piezoelectric element displaced in the track direction, enabling a fine track position control, and a piezoelectric element displaced in a magnetic disc rotation direction, enabling reduction of jitter of a reproduction signal.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: August 16, 2005
    Assignee: TDK Corporation
    Inventor: Masahiro Yanagisawa
  • Patent number: 6931609
    Abstract: In order to calculate, at high precision, capacitance parameters of an equivalent circuit model including tunnel conductances corresponding to a film thickness of a gate oxide film of an MOSFET to make reliability of device evaluation and circuit simulation improve, a computer preliminarily stores an equivalent circuit model, converts S parameter data into Y parameter data, determines whether it is possible or impossible to calculate the capacitance parameters on the basis of a real part secondary dependent area and an imaginary part primary dependent area of a frequency characteristic of the Y parameter data, generates relational expressions for Y parameters of a two-terminal pair circuit that correspond to the equivalent circuit model, measurement conditions, and a manufacturing condition of the MOFET when it is possible to calculate the capacitance parameters, producing approximated expressions by approximation conditions corresponding to the real part secondary dependent area and the imaginary part primar
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: August 16, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Yasuhisa Naruta, Shigetaka Kumashiro
  • Patent number: 6928775
    Abstract: A multiuse electric tile module for walling, flooring, or roofing applications having a photovoltaic cell, thermovoltaic cell, electroluminescent material, or a combination of these disposed over a rigid substrate, such as ceramic. Each tile is electrically connectable through a male-to-female connecter to at least one adjacent tile without external wiring. Preferably, a sealing layer is disposed over the electrical elements and rigid substrate to seal and protect each tile. Optionally, each tile may further include an inverter to convert direct current to alternating current or a battery to store electricity. The electroluminescent material provides light for architectural accents or nighttime visibility.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: August 16, 2005
    Inventor: Mark P. Banister