Patents Represented by Attorney Hayes Soloway P.C.
  • Patent number: 6927963
    Abstract: A fault detection circuit that includes a controllable switch coupling a power source to a load. Control circuitry is provided that determines if the switch is in the proper conduction state based on a switch control signal and a signal indicative of power delivered to the load. If the switch is determined as improperly closed (conducting), the control circuitry diverts energy delivered to the load through fuse circuitry, thereby blowing a fuse and decoupling the load from the power source. In preferred embodiments, logic circuitry determines the relative states of the control switch and the load and generates a control signal to divert energy away from the load and blow a fuse.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: August 9, 2005
    Assignee: Ametek, Inc.
    Inventor: Frederick Jerome Potter, IV
  • Patent number: 6924003
    Abstract: The present invention provides a method of processing a nanotube, comprising the steps of: causing a selective solid state reaction between a selected part of a nanotube and a reactive substance to have the selected part only become a reaction product; and separating the nanotube from the reaction product to define an end of the nanotube.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: August 2, 2005
    Assignee: NEC Corporation
    Inventor: Yuegang Zhang
  • Patent number: 6924863
    Abstract: An in-plane switching mode active matrix type liquid crystal display device includes a first substrate, a second substrate located opposing the first substrate, and a liquid crystal layer sandwiched between the first and second substrates. The first substrate includes a thin film transistor, a pixel electrode each associated to a pixel to be driven, a common electrode to which a reference voltage is applied, data lines, a scanning line, and common electrode lines. Molecular axes of liquid crystal are rotated in a plane parallel with the first substrate by an electric field substantially parallel with a plane of the first substrate to thereby display certain images. The common electrode is composed of transparent material, and are formed on a layer located closer to the liquid crystal layer than the data lines. The common electrode entirely overlaps the data lines except an area where the data lines are located in the vicinity of the scanning line.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: August 2, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Shinichi Nishida, Kimikazu Matsumoto, Takahisa Hannuki, Kunimasa Itakura
  • Patent number: 6925049
    Abstract: In a wobble-format type optical recording medium 10 involving a guide groove 11 wherein the guide groove is allowed to meander over substantially the whole length thereof to form wobble, and wobbled intermittent sections 12 where there are no meandrous area are placed at predetermined positions in the wobble; a first wobbled intermittent section 12a for determining reference position is disposed at at least one reference position A in the optical recording medium, and furthermore, a second wobbled intermittent section 12b is disposed selectively at each predetermined position B apart from each reference position by a predetermined distance.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: August 2, 2005
    Assignee: NEC Corporation
    Inventor: Masatsugu Ogawa
  • Patent number: 6924856
    Abstract: A LCD device is provided. On the input side, the collimated-light generator generates collimated light from incident light and then, the first polarizer plate of the first polarized-light controller generates first polarized light from the collimated light. The first quarter wavelength plate of the first polarized-light controller generates second polarized light from the first polarized light. The second polarized light thus generated passes through the liquid crystal layer to reach the output side. On the output side, the second polarized light passes through the second quarter wavelength plate of the second polarized-light controller and the second quarter wavelength plate thereof. Thus, the polarization state of the second polarized light is returned to its original one.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: August 2, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Hiroshi Okumura, Masayoshi Suzuki
  • Patent number: 6924598
    Abstract: An apparatus for providing a visual lightning effect includes a first chamber and a second chamber, where a passageway connects the first chamber and the second chamber. An inert gas is provided within the first chamber, the second chamber, and the passageway. A first contact is located external to the first chamber; and a second contact is located external to the second chamber, wherein an electrode provides a charge to the second contact, wherein the charge causes an electrical discharge between the second contact and the first contact via channels provided by fill material located within the second chamber that traverses the passageway to the first chamber, thereby resulting in the brilliant visual lightning effect.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: August 2, 2005
    Inventor: Wayne Strattman
  • Patent number: 6923979
    Abstract: Uniform portions of fine powders are deposited on a substrate by electrostatic attraction in which the charge of the electric field and polarity of the charged particles are varied repeatedly to form a buildup of powder on the carrier surface.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: August 2, 2005
    Assignee: Microdose Technologies, Inc.
    Inventors: Richard Fotland, John Bowers, William Jameson
  • Patent number: 6924201
    Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: August 2, 2005
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Masahiro Tanomura, Hidenori Shimawaki, Yosuke Miyoshi, Fumio Harima
  • Patent number: 6920240
    Abstract: Sets of projections of measurements through an object (1) the image of which is to be represented, undergo Fourier transforms before being broken down into blocks according to cutoff frequencies. The blocks are separately reconstructed in order to form a series of thumbnail images of the object, which are then combined in order to reconstruct the final image. The reconstruction calculations on the thumbnail images are rapid and often a large portion of the blocks will be discarded, notably those which are at high frequencies, whereby their contribution may frequently be neglected as well as the noise effects which accumulate therein. The invention is applied to medical or industrial tomography methods and is of larger interest for mobile objects, the movement of which may be estimated and compensated.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: July 19, 2005
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Thomas Rodet, Pierre Grangeat, Laurent Desbat
  • Patent number: 6918172
    Abstract: A niobium-based superconductor is manufactured by establishing multiple niobium components in a billet of a ductile metal, working the composite billet through a series of reduction steps to form the niobium components into elongated elements, each niobium element having a thickness on the order of 1 to 25 microns, surrounding the billet prior to the last reduction step with a porous confining layer of an acid resistant metal, immersing the confined billet in an acid or a high temperature liquid metal to remove the ductile metal from between the niobium elements while the niobium elements remain confined by said porous layer, exposing the confined mass of niobium elements to a material capable of reacting with Nb to form a superconductor.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: July 19, 2005
    Assignee: Composite Materials Technology, Inc.
    Inventor: James Wong
  • Patent number: 6919869
    Abstract: A control circuit receives the digital input data of n-bit and controls horizontal drivers so as to provide a liquid crystal panel with voltage corresponding to the input data during a 1H cycle based on standard voltage. In addition, the control circuit creates gradation data by inverting each bit of the input data and controls the horizontal drivers so as to provide the liquid crystal panel with voltage in response to the output gradation data during the subsequent 1H cycle. In this case, gradation-? correction voltage relation is symmetrical with respect to a point in the center between the top gradation step and the bottom gradation step.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: July 19, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Fumitake Yoshikawa
  • Patent number: 6919596
    Abstract: A lower electrode in a capacitive element area is formed on a field oxide film in self-alignment with trenches, so that the lower electrode and floating gate electrodes in a memory cell area can simultaneously be formed in one process. The lower electrode is surrounded by the trenches defined in the field oxide film. An upper electrode formed together with a control gate electrode in one process is disposed over the lower electrode with an insulating film, which is formed together with an intergate insulating film in the memory cell area in one process, interposed therebetween. With this arrangement, a semiconductor device having a capacitive element for use in a charge pump circuit or the like has its chip area prevented from being increased, allow the capacitive element to have a highly accurate capacitance, and can be manufactured in a reduced number of fabrication steps.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: July 19, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Hideki Hara, Kazuhiko Sanada
  • Patent number: 6913487
    Abstract: For the purpose of transmitting signals without interfering radiation, a plug-in connector module is proposed which comprises an electrically conductive shell-type casing, with a connector insert, in a retaining body composed of insulating material. The plug-in connector module is held by locking device in a module mounting device which, in turn, is integrated into a plug-in connector casing. Within the shell-type casing, an electrically conductive contact with the shielding of a signal-carrying cable is provided, so that it is possible to dispose in the module mounting device, without mutual interference, both a plurality of plug-in connector modules having mutually independent earth potentials and plug-in connector modules which transmit a power supply, pneumatic supply or suchlike.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: July 5, 2005
    Assignee: Harting Electric GmbH & Co. KG
    Inventors: Andre Beneke, Heiko Meier, Uwe Sundermeier
  • Patent number: 6912186
    Abstract: In a method of recording or reproducing data out of an optical disk of the present invention, the optical disk is includes a substrate formed with a spiral groove track and a land track formed between nearby portions of the groove track. Header information is periodically recorded in each of the groove track and land track. Beam spots are formed on the land track and groove at the same time. Data are recorded in or reproduced out of the land track and groove track at the same time on the basis of a timing determined by the header information read out of the land track and groove track. When one beam spot formed on either one of the land track and groove track is reading the header information, the other beam spot is inhibited from recording or reproducing data.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: June 28, 2005
    Assignee: NEC Corporation
    Inventor: Yutaka Yamanaka
  • Patent number: 6911096
    Abstract: A method of collecting impurities existing on the surface of a semiconductor wafer and in a thin film formed on the semiconductor wafer is provided with a process for dripping collecting liquid on the surface of the semiconductor wafer to which hydrophobic processing is applied, a process for elongating the collecting liquid dripped and turned spherical by surface tension in a direction of the radius of the semiconductor wafer with the surface tension kept, a process for relatively rolling and scanning the elongated collecting liquid, touching the collecting liquid to the surface of the semiconductor wafer and incorporating impurities into the collecting liquid, a process for restoring the elongated collecting liquid to the original spherical shape after the impurities are incorporated and a process for withdrawing the collecting liquid restored to the spherical shape from the surface of the semiconductor wafer.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: June 28, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Kaori Watanabe
  • Patent number: 6908325
    Abstract: The invention relates to a plug-in jack comprising an insulating jack housing in which at least one jack contact is accommodated. The jack contact consists of a retaining part and a jack, the jack being mounted on the retaining part so as to be pivotable by a limited angle. The invention further relates to a plug part having an insulating plug housing in which there is accommodated at least one plug contact provided for engaging into the jack contact of the plug-in jack.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: June 21, 2005
    Assignee: Harting Electronics GmbH & Co. KG
    Inventors: Jean Francois Bernat, Jean-Merri de Vanssay
  • Patent number: 6905262
    Abstract: A semiconductor device for optically coupling a semiconductor light-emitting device to an optical fiber, includes (a) a lens which focuses lights emitted from the semiconductor light-emitting device, onto the optical fiber, (b) a shell which supports the lens therewith, the shell being comprised of a cylindrical first portion, a second portion integral with the first portion at an upper end of the first portion and being formed centrally with an opening into which the lens is to be fit, and a cylindrical third portion extending from the first portion upwardly beyond the second portion, (c) glass arranged around the lens for keeping the lens and the opening hermetically sealed, and (d) a reinforcement formed on at least one of upper and lower surfaces of the second portion for preventing the shell from being deformed due to a stress acting on the shell.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: June 14, 2005
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventor: Tetsu Yoshizawa
  • Patent number: 6902844
    Abstract: A film-sealed nonaqueous electrolyte battery comprises: a battery element including a non-aqueous electrolyte; a film case having at least a sealant polymer resin film for sealing the battery element; at least a lead terminal extending from the battery element and projecting from the film case, and the lead terminal with a surface having a contact area in contact directly with the sealant polymer resin film, and at least the contact area of the surface of the lead terminal is coated with an anti-corrosion coating film, wherein the anti-corrosion coating film includes: (A) a polymer of structural units of a phenolic compound, and at least a part of the structural units includes a substituent which comprises an amino group or a substituted amino group; (B) a phosphate compound; and (C) a titanium fluorine compound.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: June 7, 2005
    Assignees: NEC Corporation, NEC Tokin Corporation, Nihon Parkerizing Co., Ltd.
    Inventors: Hiroshi Yageta, Hidemasa Kawai, Masato Shirakata, Tetsuya Takashima, Ikuo Kojima, Norihide Ohyama, Hiroyuki Iizuka
  • Patent number: 6900859
    Abstract: An in-plane switching mode active matrix liquid crystal display panel includes a substrate structure having a black matrix defining openings and color filter layers disposed in the openings, another substrate structure formed with thin film transistors, pixel electrodes and common electrodes for generating local lateral electric fields and liquid crystal filling the gap between the substrate structures, wherein a highly resistive layer is inserted in the gap between the black matrix and the color filter layers for blocking the color filter layers from electric charges induced in the black matrix due to a potential variation on the pixel electrodes, thereby preventing the visual images from an after image and irregularity in colors.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: May 31, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Kimikazu Matsumoto
  • Patent number: 6900689
    Abstract: A CMOS reference voltage circuit, preferably formed on a semiconductor integrated circuit, and outputting a reference voltage having a temperature-independent characteristic, comprises first and second diode-connected transistors (or diodes), respectively grounded and driven with two constant currents bearing a constant current ratio to each other, and a unit for amplifying a differential voltage of output voltages from the first and second transistors by a preset factor and for summing the amplified differential voltage to an output voltage of the first or second transistor. The amplifying and summing unit is formed by two OTAs 11, 12 and a current mirror circuit 13.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: May 31, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Katsuji Kimura