Abstract: A timing-driven layout method is provided, which realizes timing error convergence toward zero without any timing constraint file. (a) An initial layout result is generated through placement of functional blocks of the circuit and routing of wiring lines therefor. (b) Wiring capacitance values of the respective blocks are calculated using the initial layout result. (c) Fan-out capacitance limitation values of the respective blocks are calculated using the wiring capacitance values of the blocks. Each of the fan-out capacitance limitation values represents a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value. (d) A driving capability of each of the blocks is compared with its fan-out capacitance limitation value, thereby generating a comparison result.

Abstract: A clasp apparatus to releaseably hold an ornamental object. That ornamental object may have a spherical shape or an irregular shape. A method to releaseably hold an ornamental object.

Abstract: A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

Abstract: A circular-shaped metal structure formed by spinning working has a thickness equal to or smaller than 0.09 mm. The structure may be used as a photosensitive drum or fixing belt in an electrophotographic printer.

Abstract: An alignment pattern is required for photo masks to be exactly aligned with one another; an amorphous silicon is deposited over the entire surface of an insulating layer except for an area where the alignment pattern is to be formed, and a pattern for an ion-implantation and the alignment pattern are concurrently transferred to a photo resist layer; dopant impurity is ion implanted into the amorphous silicon layer by using the photo resist mask, and the insulating layer is selectively etched also by using the photo resist mask; this results in simplification of the process sequence.

Abstract: An apparatus for processing particulate dust when a substrate is arranged in a high vacuum enclosure, plasma is generated in the high vacuum enclosure, and a reactive material is introduced into the high vacuum enclosure to perform processing of the substrate. At least one collecting electrode is provided around the substrate in the high vacuum enclosure other than the electrode that generates plasma, and particulates generated in plasma are efficiently removed by applying a predetermined electric potential of a direct-current or an alternating current to the collecting electrode, and thus a deposition problem onto an inner wall of the vacuum enclosure and a deterioration problem of processing accuracy and a film quality associated with flowing of the particulates onto the substrate are solved.

Abstract: An output buffer circuit has a main driver including a first pMOS transistor and a first nMOS transistor for driving a load, and a second pMOS transistor and a second nMOS transistor for driving the load in coaction with the first pMOS transistor and the first nMOS transistor, and a predriver including a third pMOS transistor and a third nMOS transistor for driving the first pMOS transistor, a fourth pMOS transistor and a fourth nMOS transistor for driving the first nMOS transistor, a fifth nMOS transistor for driving the first pMOS transistor in coaction with the third nMOS transistor, and a fifth pMOS transistor for driving the first nMOS transistor in coaction with the fourth pMOS transistor.

Abstract: A semiconductor device adopting shallow trench isolation for reducing an internal stress of a semiconductor substrate. The semiconductor device is composed of a semiconductor substrate provided with a trench for isolation, and an insulating film formed to cover the trench for relaxing an internal stress of the semiconductor substrate. The insulating film includes a first portion disposed to be opposed to a bottom of the trench, and a second portion disposed to be opposed to a side of the trench. A first thickness of the first portion is different from a second thickness of the second portion.

Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.

Abstract: The batch projection regions and of an electron beam projection mask are arranged so that pattern density may be equalized on the whole wafer surface.

Abstract: A porous wall through which a flow of gas is established forming a layer supporting a liquid mass is strengthened partly to stiffen it and partly to control the shape of the lower surface of the supported liquid. Chambers containing different pressures can be formed, and possibly, separated by some of these strengthening parts to improve the equalisation by reducing the pressure at the center. Finally, capillaries may pass through the plate to measure the pressure or provide additional equalisation of the thickness of the layer by a suction device.

Abstract: A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

Abstract: In a semiconductor memory, a barrier layer formed of a first metal film, a metal nitride film and a second metal film laminated in the named order is formed under a lower electrode of a ferroelectric capacitor in a memory cell, in order to minimize a pealing and lifting of the lower electrode from an underlying plug in the process of forming a ferroelectric material film as a capacitor dielectric film and in its succeeding annealing process. The metal nitride film is formed of a nitride of a metal constituting the first or second metal film.

Abstract: A method for compensating track offset in an optical disk drive is provided, which achieves complete compensation of the track offset and than reduces the compensation time for the track offset. (a) An optical disk with wobbled grooves is provided, the wobbled grooves being used for generating a wobbling signal with a wobbling period. (b) A beat-inducing signal is recorded on the disk. The period of the beat-inducing signal has a specific relationship with the wobbling period in such a way that a beat signal is induced by the beat-inducing signal and the wobbling signal. (c) A tracking-error signal is generated using a push-pull method by optically reading the wobbled grooves of the disk and the beat-inducing signal recorded on the disk. The tracking-error signal contains a beat signal induced by the beat-inducing signal and the wobbling signal. (d) Track offset is compensated based on the beat signal contained in the tracking-error signal.

Abstract: A multiplexer cell layout structure is a layout structure of primitive cells where cell arrays composed of P-channel transistors and N-channel transistors are arranged in two upper and lower rows. And, a plurality of transistors of transfer gates are arranged on the upper side and lower side of the cell arrays, an output terminal of the plurality of arranged transistors is connected up and down by Metal wiring across between the upper and lower cell arrays. Thus, a multiplexer cell layout structure which increases wiring tracks of two-layer metal wiring for a one-chip layout held by a 4-input multiplexer inverter can be obtained.

Abstract: To provide a fingerprint input device including a collected fiber member that is brought into intimate contact with a fingerprint surface of a finger, a planar light source for illuminating said fingerprint surface, and a two-dimensional image sensor for detecting a light reflected from the fingerprint surface and a light scattered in the finger and emitted from the fingerprint surface, the two-dimensional image sensor having a plurality of photoelectric conversion element arranged two-dimensionally on a substrate. The fingerprint input device detects a fingerprint image and a plethysmogram or acceleration plethysmogram by switching between a mode, in which electric signals produced in the plurality of photoelectric conversion elements are output simultaneously, and a mode, in which electric signals produced in the plurality of photoelectric conversion elements are output sequentially.

Abstract: The contact resistance of each switch is reduced, and the on-resistances of all of the switches are set to be uniform, while the area required for arrangement of bit line selection switches is not increased. The switches are connected to one-side ends of the bit lines provided at the odd-numbered positions, and are connected to the other-side ends of the bit lines provided at the even-numbered positions. A pair of odd-numbered or even-numbered bit lines are connected to the terminals of each sense amplifier, respectively. The memory cells are arranged at predetermined intersection points of the word lies and the bit lines, the number of the predetermined intersection points being equal to half of all the intersection points thereof, in such a manner that when one word line is selected, the memory cells connected to the selected word-line can be electrically connected in such a manner that one memory cell is electrically connected to each terminal of the unit circuits.

Abstract: A reactor of a chemical vapor deposition system is equipped with a gas feeder for blowing dopant gas to plural semiconductor wafers supported by a wafer boat at intervals, and the gas feeder has a gas passage gradually reduced in cross section and gas outlet holes equal in diameter and arranged along the wafer boat for keeping the doping gas concentration substantially constant around the semiconductor wafers, whereby the dopant is uniformly introduced in material deposited on all the semiconductor wafers.

Abstract: In the present invention, solid contents 38, which are collected by a solid-liquid separation device 33 in a solid-liquid separation tank 14 and charged into a decomposing treatment tank 11, are decomposed to water and CO2 by the action of aerobic microbes and the air (oxygen) supplied from a lower aeration tank 12 and substantially disappear. The oil contents contained in the water having been decomposed is removed by an oil-water separation tank 13.

Abstract: A signal line of a data bus includes first wires on a first board and a second wire on a second board. The second board is installed on the first board to connect the first and second wires with each other in series to establish the signal line. Semiconductor devices are connected with the second wire. In such data bus system, impedance of the second wire is decided according to additional capacitance of the semiconductor device on the second board in order to harmonize impedance of the first board with impedance of the second board.