Abstract: The present invention discloses a semiconductor memory device having a multilevel interconnection structure with no conventional limitation on the number of lines. The semiconductor memory device has a multilevel interconnection structure in which column selection lines extending in the Y direction and main word lines extending in the X direction are arranged in different layers. The layer including the column selection lines is disposed under the layer including the main word lines. In the structure, in sub-word driver areas intersecting the X direction, the main word lines are arranged in a top layer and sub-word selection lines are arranged in a layer lower than the top layer. The lower layer includes a pattern of islands. According to this interconnection structure, the number of islands can be reduced. Consequently, a plurality of power lines can be arranged between the adjacent main word lines in the sub-word driver areas.

Abstract: A first counter counts a first clock signal repeatedly in accordance with an external synchronous signal. A second counter counts a second clock signal repeatedly in every predetermined cycle, and generates an internal synchronous signal having the predetermined cycle. A controller adjusts the cycle of counting performed by the second counter by controlling the second counter. By doing so, the controller controls the internal synchronous signal to synchronize with the external synchronous signal in each horizontal period.

Abstract: A unit test signal having duration T is repeatedly supplied from an LSI tester to an IC under test and, simultaneously, a power source current is supplied from the LSI tester through a current detection unit to the IC under test. The power source current is monitored by the current detection unit and a current information obtained by the monitoring is analyzed by a spectrum analyzer unit. Since the repetition period of the test signal is T, the power source current having a period nT flows through the IC under test along with a state shift of the IC under test, where n is an integer. When the IC under test has a fault, the power source current flows with a period n′T, where n′ is an integer different from n, or an abnormal power source current flows with the period nT, due to a change of the state shift of the IC under test.

Abstract: A semiconductor device includes a lower wiring layer, a first insulating layer formed on the lower wiring layer and having a via hole with a width, a via mask layer formed on the first insulating layer and having an opening with a width larger than the width of the via hole, a second insulating layer formed on the via mask layer and having an upper wiring, groove whose width coincides with the width of the via hole, a via contact structure buried in the via hole, and an upper wiring layer buried in the upper wiring groove.

Abstract: An in-plane switching type liquid crystal display device includes (a) a first film composed of inorganic material, (b) a second film composed of organic material, both of the first and second films being to be formed below an electrode as underlying films, (c) a first vernier formed on the first film for measuring a width of the electrode, and (d) a second vernier formed on the second film for measuring a width of the electrode.

Abstract: There is provided a method of driving a solid-state image sensor, including the steps of transferring signal charges from photoelectric transfer devices to vertical CCDs constituted of a plurality of pixels, when a pulse is applied to the pixel, the pulse being applied to the pixels in at least two pixel lines so that a trailing edge of a first pulse to be applied in a first pixel line corresponds with a leading edge of a second pulse to be applied in a second pixel line, transferring the signal charges from the vertical CCDs to a horizontal CCD, and outputting the signal charges from horizontal CCD to an external circuit. The method makes it possible to prevent an increase in a substrate voltage at which charges are reversely transferred to photodiodes, which increase is caused by simultaneously applying pulses to all signal readers.

Abstract: A bone grafting and/or shaping instrument includes a handle portion, a collection chamber and a blade. Features on the blade cooperate with features on the collection chamber to secure the blade to the collection chamber. A flexible joint between the collection chamber and the handle portion allows the user to orient the cutting edge of the blade in any desired position relative to the handle portion.

Abstract: In a processor executing plural instructions simultaneously, writin-destination-register numbers of the plural instructions to be executed simultaneously are compared, and kinds of operations to be executed by the plural instructions are changed in response to a comparison result. When the writing-destination-register numbers of the plural instructions are identical, a constant operation is applied to plural operation results obtained from the plural instructions to obtain an operation result and the operation result is written into the writing-destination-register instructed by the plural instructions. Results outputted from plural processing units are put together into one result and the result is stored in one register. Thus, register use efficiency and process efficiency are improved.

Abstract: A process for transfer of at least one thin film of solid material delimited in an initial substrate. The process includes a step in which a layer of inclusions is formed in the initial substrate at a depth corresponding to the required thickness of the thin film. These inclusions are designed to form traps for gaseous compounds which subsequently are implanted. In a subsequent step gaseous compounds are implanted in a manner to convey the gaseous compounds into the layer of inclusions. The dose of implanted gaseous compounds is made sufficient to cause the formation of micro-cavities to form a fracture plane along which the thin film can be separated from the remainder of the substrate.

Abstract: A bump is formed at a predetermined position on a surface of a semiconductor wafer and a sealing resin is formed so as to cover the surface and to make a surface of the bump exposed. Then, a reinforcing plate is bonded to the sealing resin and the exposed surface of the bump through an adhesive, and a rear portion of the semiconductor wafer is ground using a grind stone or removed by wet etching. Then, the rear surface of the thinned semiconductor wafer is covered with another sealing resin.

Abstract: For connection elements, which are designed as pin contacts or contact tubes and disposed in an insulating housing, for the electrical contacting of the respective connection ends with an electrical conductor having a plurality of strands it is proposed to provide the connection ends with a structure, which is shaped in a saw-tooth-like manner and is surrounded by a slotted sleeve, wherein into the slot of the latter a wedge element is insertable so that, in the open state of the sleeve, the strands are insertable into the gap between saw-tooth contour and sleeve and, when the wedge element is removed, the strands are pressed into the saw-tooth contour by the resiliently designed sleeve.

Abstract: Iso-&agr;-acids and reduced iso-&agr;-acids in their free acids states are converted into mobile resins by the addition of concentrated solutions of alkali metal hydroxides. The products may be used in brewing for the bittering of beer and are most effectively used in an apparatus that automatically blends the product with water and injects the resultant, aqueous solution into beer.

Abstract: A VA (Vertical Aligned) type active-matrix liquid crystal display capable of stabilizing a boundary position between divided areas (alignment areas). The liquid crystal display comprises a TFT (thin film transistor) substrate including a pixel electrode provided for each pixel and a driving element such as a TFT provided for each pixel electrode, an opposite substrate disposed opposite to the TFT substrate and including an opposite electrode, and a liquid crystal layer sandwiched between the TFT substrate and the opposite substrate. Each pixel electrode has a recess in groove shape formed therein. The pixel electrode preferably has a generally rectangular shape. The recess is provided such that it extends from one of a pair of opposite sides of the pixel electrode to the other to divide the pixel electrode into two parts.

Abstract: The present invention provides a DLL and a semiconductor integrated circuit device of reduced power consumption suited for use in equipment that complies with DDR-II specifications. It also provides a DLL and a semiconductor integrated circuit device in which the occurrence of hazards at the time of tap changeover is suppressed, thereby preventing a deviation in output timing as well as malfunction. In accordance with one aspect of the present invention, a delay-locked loop device is provided for adjusting delay times of serially connected first and second delay lines in such a manner that a signal obtained by delaying an input signal by the first and second delay lines is in phase with the input signal, thereby outputting, from the first delay line, a signal that is the result of delaying the input signal by one half cycle of the input signal.

Abstract: The invention is directed to an electronic parking meter and a method of configuring an electronic parking meter. In addition to a meter housing and an electronic metering mechanism within the housing, the parking meter includes a memory positioned within the housing separate from the electronic metering mechanism for storing configuration information associated with a pre-selected group of one or more electronic meters. When the electronic metering mechanism is replaced, the replacement metering mechanism that is inserted into the housing need only be coupled to the separate memory in order to have the configuration information of the specific meter downloaded into it. The configuration information includes parking meter location information and/or parking restriction information.

Abstract: A method and apparatus for producing printed circuits utilizing direct printing methods to apply a pattern mask to a substrate. The pattern mask may be an etch resist mask for forming conductive pathways by an etching process, or the pattern mask may be a plating mask with conductive pathways being formed by a plating operation. The process of the present invention is applicable to forming both single-sided and double sided printed circuit boards.

Abstract: In an in-plane switching (IPS) mode active matrix type liquid crystal display device, data lines 24 supplied with data signals, common electrode wiring portions 26a and 26b applied with a reference voltage, a common electrode 26, pixel electrodes corresponding to pixels to be displayed, scanning lines 28 supplied with scan signals and TFT's 50 are provided on an active element substrate 11. The common electrode wiring portions 26a and 26b are formed by using a first metal layer, extend in parallel to the scanning line and connected to a common electrode potential at a peripheral portion thereof. Protruded portions 299a and 299b are formed in at least one of the common electrode wiring portions 26a and 26b in such a way that the protruded portions are positioned on both sides of the data line 24 to be formed later. Unevenness of display of the display device is reduced and the aperture ratio thereof is improved.

Abstract: A novel clock control circuit and method in which phase synchronization with respect to an external clock can be realized without recourse to the external clocks. A clock controlling circuit includes a delay circuit sequence comprised of N stages of units each made up of a first delay circuit 10 and a first interior division circuit 11 for delaying the output signal of the first delay circuit, and a phase difference detection circuit 14 for detecting the clock period and the delay time difference of the delay circuit sequence from the input clock IN and a clock END output by the delay circuit sequence as a phase difference of the two signals. A plural number of second interior division circuits 12, fed with an output signal of the first delay circuit, delays a transition edge of an output signal of the first delay circuit by t2−n×T/N to output the delayed signal.

Abstract: An active matrix substrate includes a substrate composed of resin, and a polysilicon thin film diode formed on the substrate. The polysilicon thin film diode may be a lateral diode centrally having a region into which impurity is doped. As an alternative, the polysilicon thin film diode may be comprised of two lateral diodes electrically connected in parallel to each other and arranged in opposite directions.