Patents Represented by Attorney Rabin & Berdo, P.C.
  • Patent number: 6775883
    Abstract: A hinge mechanism for pivotally connecting a flip onto a housing includes a bush, a compression spring, and a release button. The bush has a sidewall, a receiving space defined by the sidewall, and a protrusion. The protrusion is protruded from the sidewall. The release button has a shaped notch, which includes a concave portion, a stop portion, and a convex portion formed between the concave portion and the stop portion. The stop portion extends substantially parallel to the pivoting axis. The protrusion is slidably received within the shaped notch. The compression spring is disposed within the receiving space and pressed by the release button and the bush. When closing the flip, the bush rotates synchronously with the flip and the protrusion moves in the shaped notch. When pushing the release button, the flip opens automatically.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: August 17, 2004
    Assignee: BenQ Corporation
    Inventors: Long-Jyh Pan, Hsiao-Wu Chen
  • Patent number: 6777912
    Abstract: This invention allows storage electric power to be secured at a maximum by reducing variation in potential between a plurality of capacitors constituting an electric power storage device as follows. A plurality of capacitor banks are provided, in parallel, in the electric power storage device. A part of the respective capacitor banks is halted depending on the current flowing through the electric power storage device. Electric charge of the respective capacitor parallel circuits is individually discharged in the halted capacitor bank, thereby, the terminal voltage of the respective capacitor parallel circuits are equalized.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: August 17, 2004
    Assignee: Nissan Diesel Motor Co, Ltd.
    Inventors: Jun Yamada, Yoshiaki Yamada, Tsutomu Sasaki, Masakazu Sasaki
  • Patent number: 6777983
    Abstract: A differential voltage transmission circuit. The reference bias circuit outputs a first reference voltage, a second reference voltage and a reference current corresponding to a reference current adjusting signal. The differential comparator compares the difference between the first reference voltage and the second reference voltage with the difference between a first output voltage and a second output voltage, and outputs a result signal corresponding to the compared result. The decision circuit outputs the reference current adjusting signal corresponding to the result signal. The output circuit outputs the first output voltage and the second output voltage generated at both terminals of a termination resistor when the reference current flows through the termination resistor.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: August 17, 2004
    Assignee: Faraday Technology Corp.
    Inventors: Shin-Lin Wang, Kun-Chih Chang
  • Patent number: 6776651
    Abstract: A stacked electronic connector includes a hollow mounting block, a first type connector socket and a second type connector socket. The mounting block has a front, a rear, two opposite sides, two inner guides, defined inside the mounting block and two windows through two corners where the front and the sides of the mounting block meet. The second type connector socket has two indicator lights and two arms. Each arm has a front end and an inclined edge formed at the front end that are held in the corresponding windows. Consequently, light produced by the indicator lights will be transmitted through the arms to the front ends and the inclined edges of the arms. A person can see the light from various directions.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: August 17, 2004
    Assignee: Lankom Electronics Co., Ltd.
    Inventor: Lu-Ta Liu
  • Patent number: 6778956
    Abstract: Code patterns are first sorted in a codebook in order of power, and catalogued while preparing fixed parameters indicating a selection range size of the code patterns (not greater than values recordable in an analog flash memory), and a variable parameter indicating an offset amount of a selection range, from the leading edge of the codebook. When selecting a waveform, such selection is made from among the code patterns within the selection range, and the selection range is shifted to the optimal position by sequentially renewing the offset amount on the basis of a code number resulting from encoding of a preceding frame, and is then decided upon.
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: August 17, 2004
    Assignee: OKI Electric Industry Co., Ltd.
    Inventors: Hiroshi Sasaki, Masayasu Sato
  • Patent number: 6772660
    Abstract: Disclosed herein is means for directly coupling a main motor shaft to a working machine with a coupling head as an intermediate component. The machine unit assembled according to the present invention does not require rechecking of dimensional deviations after completion of assembly. The present invention is applicable to both upright type and lateral type machine units.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: August 10, 2004
    Assignee: Industrial Technology Research Institute
    Inventors: Chui-Hsi Tsai, Shing-Jye Hwang, Yi-Tang Chen
  • Patent number: 6773966
    Abstract: A semiconductor device manufacturing method according to the present invention comprising: arranging a dam made of a highly heat-shrinkable material on a surface of a circuit substrate, wherein the dam defines a region including a semiconductor element, a conductor, and part of a conductive pattern connected to one end of the conductor; injecting a sealer into a region defined by the dam and using the sealer to seal the semiconductor element, the conductor, and part of the conductive pattern connecting with one end of the conductor; and cooling the dam to remove it. Namely, the method can decrease costs, shorten the manufacturing time, and provide miniaturized COB-mounted semiconductor devices.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: August 10, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Seiji Andoh
  • Patent number: 6774756
    Abstract: A functional material—composite structural magnetic core is the magnetic core mainly consisting of magnetic material and having regular geometric form. It includes a box with a slot cavity and through hole. The inner magnetic core is installed inside the cavity of the box. It is characterized by: there are multiple inter-layers inside of the cavity of the slot. The inter-layers divide the slot cavity into the multiple continued ring slot and inside the ring slot many inner magnetic cores are installed respectively. The advantages are: wide application frequency band, large application temperature range, expanded electromagnetic compatibility. The continued stability and sudden change of the electromagnetic characteristics can meet requirements of the electronic technology. The sensing and sending of power transferred signal and control of noise wave etc. showed its composite excellent performance, corresponding and matching characteristics.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: August 10, 2004
    Inventor: Qiang Zhao
  • Patent number: 6774014
    Abstract: A method of fabricating a device with spherical quantum dots by a combination of gas condensation and an epitaxial technique includes the following steps: (a) a quantum dots growth step, when the quantum dots are grown on the substrate by a gas condensation method; (b) a quantum dots processing step, when an ultrasonic cleaner is used with an organic solvent to vibrate the substrate in which quantum dots have been grown in step (a), or the substrate in which quantum dots have been grown in step (a) is thermally annealed at a high temperature to obtain a thin layer of quantum dots; and (c) an epitaxial layer cover step, when an epitaxial layer is covered over the quantum dots processed by step (b) by an epitaxial technique. By virtue of the above processes, a device with completely spherical quantum dots is obtained.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: August 10, 2004
    Assignee: National Taiwan University
    Inventors: Si-Chen Lee, Tse-Chi Lin
  • Patent number: 6774708
    Abstract: A voltage boosting circuit has two charge pumps connected to an output node from which a boosted potential, higher than the power-supply potential, is supplied to a load circuit. One charge pump is activated when the load circuit is activated, regardless of the output node potential. The other charge pump is activated while the load circuit is active, if the potential of the output node falls below a predetermined level. Use of these two charge pumps reduces electrical noise and ensures that the output node is brought to an adequate potential when the load circuit is activated.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: August 10, 2004
    Assignee: OKI Electric Industry Co., Ltd.
    Inventor: Katsuaki Matsui
  • Patent number: 6775208
    Abstract: The present invention provides a method for controlling a focus speed of a pick-up head while performing a layer jump operation over a multi-layer optical disk in an optical information reproducing apparatus. The optical information reproducing apparatus includes the pick-up head, an actuator and a counter. The pick-up head has an objective lens positioned over a first focus of the multi-layer optical disk and in response to a signal reflected from the multi-layer optical disk, will generate a RF level signal and. The actuator is electronically connected to the pick-up head for driving the objective lens to perform the layer jump operation in response to a kick pulse signal. The counter generates a counter value in response to the kick pulse signal.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: August 10, 2004
    Assignee: Asustek Computer Inc.
    Inventors: Ching-Hwa Liu, Chun-Hsiang Tsai, Wei-Hsin Hsu
  • Patent number: 6773991
    Abstract: Heavily concentrated impurities are selectively introduced into an exposed region of an oxide film. The exposed region of the oxide film where the impurities are introduced is selectively etched so that a surface of the semiconductor substrate is exposed An oxidizing process is performed and a second oxide film is formed on the first oxide film and the exposed surface of the semiconductor substrate. A polysilicon layer is formed as the floating gate.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: August 10, 2004
    Assignee: Oki Electric Industry Co, Ltd.
    Inventor: Toshiyuki Orita
  • Patent number: 6775135
    Abstract: A heat isolation apparatus is described. The heat isolation apparatus prevents an equipment surface from being heated to a high temperature by a heat source. The apparatus is especially employed for the heat source, such as an integrated circuit, in a notebook computer. The heat isolation apparatus comprises an inlet, an isolation wall, and an outlet. The inlet sucks in fresh air. The isolation wall formed by hollow structure delivers the fresh air to the outlet. The isolation wall separates the heat generated by the heat source on one side and reduces the temperature on the other side thereof. The heat isolation apparatus further connects with a fan. One end, near the fan, of the heat isolation apparatus further has a smooth, curves shape to smooth the floating fresh air.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: August 10, 2004
    Assignee: Quanta Computer Inc.
    Inventor: Li-Chun Lo
  • Patent number: 6774850
    Abstract: A broadband couple-fed planar antenna including radiating strips on the ground plane. Plural radiating strips are electrically connected to a ground plane and are formed on the same plane of the ground plane. The radiating strip has a first segment extended from an edge of the ground and a second segment bend at an angle connected to the first segment. The couple-fed planar antenna has a feeding line coupling signals to the radiating strips. The number of the radiating strips is flexible for the required bandwidth of the couple-fed plannar antenna.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: August 10, 2004
    Assignee: High Tech Computer, Corp.
    Inventor: Kuo-Cheng Chen
  • Patent number: 6774875
    Abstract: A method for compensating luminance, suitable for use in a plasma display panel. The method includes the following steps. First, the luminance value of each pixel signal is read out. Then, the load of the pixel signal row is computed. The load is the number of pixel signal in the pixel signal row that the luminance value of the pixel signal is larger than a predetermined threshold luminance value. Then, a primary luminance compensation value is decided according to the load of the pixel signal row. A number of secondary luminance compensation values are decided according to the primary luminance compensation value. Afterwards, each pixel signal in the pixel signal row is performed luminance compensation sequentially. If the luminance value is larger than or equal to a low threshold luminance value, the luminance value is subtracted by the primary luminance compensation value.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: August 10, 2004
    Assignee: AU Optronics Corp.
    Inventors: Shu-Rong Tong, Tu-Hao Tsai, Jih-Fon Huang
  • Patent number: 6773937
    Abstract: In a method to verify a mask for a mask ROM, a serial of random codes that are exclusive to each other are implanted into a plurality of wafers manufactured by a same process with the mask or a plurality of die regions in a single wafer manufactured by a same process with the mask, and then the test results derived from the implanted wafers or die regions are compared to determine if the mask is defective.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: August 10, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Lien-Che Ho, Ming-Yu Lin, Chiu-Hua Chung
  • Patent number: 6775310
    Abstract: On a semiconductor substrate (1), a double hetero structure portion (6) in which an active layer (4) having smaller band gap is sandwiched between semiconductor layers (3, 5) having larger band gap than that of the active layer (4) is formed. A light reflection film (9) is formed at least a part of side walls of the double hetero structure portion (6). As a result, a semiconductor light emitting device that light which leaks from side wall of light emitting area in a chip is reduced and emission light can be outputted efficiently can be obtained.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: August 10, 2004
    Assignee: Rohm Co., Ltd.
    Inventors: Hironobu Sai, Jun Ichihara
  • Patent number: 6772240
    Abstract: A method for saving register space in a conventional high-level function call process. The method essentially places parameters starting from either of two ends of a sequence of registers for parameter pass, based on data length, thereby reducing register waste and increasing the utility of registers when a function call is coded by a high-level compiler. Thus, the compiler for a high-level program can effectively perform the function call pass.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: August 3, 2004
    Assignee: Faraday Technology Corp.
    Inventor: Yu-Chi Chung
  • Patent number: D494411
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: August 17, 2004
    Assignee: Homeasy Enterprise Limited
    Inventors: Kah Hee Heng, Kin Man Tse
  • Patent number: D494689
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: August 17, 2004
    Assignee: Mass Technology (H.K.) Limited
    Inventor: Onn Fah Foo