Abstract: An arrangement and a method are described for the transmission of address, instruction and/or data telegrams from a control unit to (at least) one controlled unit and for the return of a respective reception acknowledge signal from the controlled unit (units) to the control unit in response to each address, instruction and/or data telegram, the reception acknowledge signal signaling the control unit the correct transmission of the relevant address, instruction and/or data telegram.

Abstract: A high-frequency amplifier circuit includes an amplifying transistor and a driver transistor, with the amplifying transistor being connected in either a common emitter or a common source configuration and the driver transistor being connected in a corresponding common collector or a common drain configuration, depending upon whether bipolar or field effect transistors are used. A current-mirror bias circuit is coupled between an input terminal and an output terminal of the driver transistor, with a resistor being provided for coupling the current mirror to the input terminal of the driver transistor. The resistor, which typically has a value of between about 20 and 100 ohms, provides a negative impedance cancellation effect while minimizing power consumption at low bias levels.

Abstract: The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly.

Abstract: A semiconductor device with a semiconductor body (1) provided with a memory capacitor (12, 26) with a lower electrode (11, 23) consisting of a layer of semiconductor material (7, 23) having a rough surface (8, 24) formed by hemispherical grains (9, 25) of the relevant semiconductor material on which a dielectric layer (12, 27) and an upper electrode (13, 28) are provided. The semiconductor material from which the lower electrode is manufactured is Si1−xGex, wherein 0.2<x<1. The semiconductor device can be manufactured in a simple manner because a layer of Si1−xGex having a rough surface formed by hemispherical grains of this material can be simply directly formed through deposition by means of usual CVD (Chemical Vapor Deposition) processes.

Abstract: The invention relates to a solid-state imaging device (1) which is encapsulated in a ceramic package covered by a transparent window (6) comprising a phosphorus-containing glass. The window is provided with a coating (8), for example of chromium, at the circumference of the window to counteract degradation of the joint between the window and the ceramic package, which degradation results from the sensitivity of phosphorus glass to moisture. The use of phosphorus glass has the advantage that it is opaque to infrared radiation, so that the application of a separate coating serving as an IR filter is avoided and hence the dependence of the sensitivity of the imaging device on the angle of incidence of the radiation to be detected.

Abstract: A thin layer SOI high-voltage device in which the drift charge is depleted using a three-dimensional MOS capacitor structure. The drift region of the high-voltage semiconductor device is doped with a graded charge profile which increases from source-to-drain. The drift region is physically patterned to create a stripe geometry where individual SOI stripes. Each SOI stripe is individually circumscribed longitudinally by a dielectric layer wherein each dielectric layer is longitudinally circumscribed by field plates of a conducting multi-capacitor field plate layer which is electrically shorted to the substrate. The resultant structure is a thin drift-region stripe which is completely enclosed by a MOS field plate, resulting in three-dimensional depletion upon application of a bias voltage between the SOI stripe and its encapsulating field plates.

Abstract: A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifier transistor to obtain a conduction angle of at least about 180°. The dc bias circuit includes a self-bias boosting circuit which has a cascode current-mirror circuit having an output coupled to a control terminal of the amplifying transistor by a resistor, and a capacitor coupled from the cascode current-mirror circuit to a common terminal. The value of the capacitor can be selected to obtain the desired amount of self-bias boosting.

Abstract: A power switching circuit has: first and second voltage supply lines (2 and 3); a control signal input terminal (I); a load terminal (LT); and a measurement terminal (MT). A power semiconductor switch (M) has a main current carrying section (MC1 and MC2) and a sense current carrying section (SC1 and SC2) for carrying a current which is proportional to and smaller than the current carried by the main current carrying section. The main current carrying section is formed of a plurality of subsidiary current carrying sections (MC1 and MC2). Each subsidiary current carrying section has a subsidiary main current carrying electrode (S1 and S2) coupled to the load terminal (LT) so that the subsidiary electrodes together form the main current carrying electrode. Each subsidiary main current carrying section has a respective different control electrode (G1 and G2).

Abstract: A thin film capacitor is provided with a thin film protection element to protect the capacitor from damage that can result due to the occurrence of an electrostatic discharge event. The thin film capacitor includes two conductive film portions forming capacitor plates and a dielectric film forming the capacitor dielectric. The protection element may take the form of a thin film diode or a series of thin film diodes connected electrically in parallel with the thin film capacitor. The whole device can be fabricated using a stoichiometric silicon nitride layer to produce the capacitor dielectric and a non-stoichiometric silicon rich silicon nitride layer to provide the diode semiconductor material. One diode is formed by one capacitor plate, the semiconductor layer and an upper diode contact.

Abstract: A multi-mode modular pulse-width-modulator capable of outputting low-speed and high-speed control signals is presented. The operation of the modulator is determined by parameters that are stored within the modulator and provide for high-speed updating and control capability in response to changes in voltage or current. In one mode, an update and control signal is generated based on timing parametric data stored in a local memory. In a second mode, an update and control signal is generated based on timing parametric data that provided by an external input device. Furthermore, control variables are also stored locally which control the position of switches, which alter signal paths within the modulator.

Abstract: The invention describes an improvement of a demodulation filter for use in a push-pull amplifier. Known demodulation filters have the disadvantage that in the common mode they have a peaking and oscillating loop introducing great distortions. The demodulation filter according to the invention overcomes these disadvantages by introducing a common mode damping without influencing the differential mode.

Abstract: The invention relates to a semiconductor device (10) comprising a semiconductor body (11) including, in succession, a first and a second semiconductor region (1, 2) of a first conductivity type having, respectively, a high and a low doping concentration, and including a third semiconductor region (3) of a second conductivity type, opposed to the first conductivity type, having a high doping concentration, whereby at least in the second semiconductor region (2) the lifetime of the charge carriers is reduced, and the first and third semiconductor region (1, 3) are provided with, respectively, a first and a second connection conductor (4, 5). According to the invention, the thickness of the second semiconductor region (2) is reduced to below 20 &mgr;m, and the service life of the charge carriers in the second semiconductor region (2) is reduced to below 20 nsec. This device is characterized by its high speed, its suitability for low-voltage applications and its surprisingly low forward voltage drop.

Abstract: A switch circuit for battery-powered equipment, for example a mobile telephone or a portable computer, comprises a 4-terminal bi-directional semiconductor switch (M1) and a protection diode (Dbg). The switch (M1) has a control-gate terminal (g) for applying a control signal (Vg) to form a conduction channel (12) in a body region (11) of the switch, for turning the switch (M1) on and off between a battery (B) and a power line (2) of the equipment. The switch (M1) also has a back-gate terminal (b; bg) in a bias path that serves for applying a bias potential (Vmin) to the body region (11). The protection diode (Dbg) has a diode path in series with the back-gate terminal (b; bg) so as to provide in the bias path a rectifying barrier (25; 25′) that blocks current flow between the body region (11) and the gate-bias terminal (b, bg) in the event of a reverse voltage polarity across the switch (M1), for example when recharging the battery (B).

Abstract: An electrical circuit arrangement (19), comprising an output stage (4) having an output terminal (2) for delivering an output current, and at least one feedback circuit (15, 16) operatively connected to the output terminal (2). A current generator circuit (20), arranged for generating a current which is a fraction of the output current, connects by a resistive element (21) to the output terminal (2), thereby providing improved high frequency feedback stability.

Abstract: To maximize the throughput and minimize the latency associated with communications among devices on a single channel communications system, this invention provides a method and apparatus for a fairness based protocol that assures each device an equal opportunity to access the single channel communications system. The protocol forces a “fairness” delay between each sequential transmission from a device, thereby allowing another device to gain access to the communications channel during this fairness delay period. In a preferred embodiment, the duration of each transmission is limited, thereby providing a maximum latency period for a device to gain access to the communications channel, and a minimum bandwidth allocation to the device. By providing a protocol having a guaranteed minimum bandwidth and maximum latency, a device in accordance with this invention need only contain the storage resources needed for the latency period.

Abstract: In a field-effect semiconductor device, for example a power MOSFET, a body portion separates a channel-accommodating region from a drain region at a surface of a semiconductor body. This body portion includes a drift region which serves for current flow of charge carriers of a first conductivity type from the conduction channel to the drain region, in a conducting mode of the device. Instead of being a single region, the body portion also includes field-relief regions of the second conductivity type, which are depleted together with the drift region in a voltage blocking mode of the device to provide a voltage-carrying space-charge region. The drain region extends at least partially around the body portion at the surface, and the relief regions are located radially in this body portion.

Abstract: The invention relates to a semiconductor device with a diode. The semiconductor body (10) comprises a stack of a first semiconductor region provided with a first connection conductor (5) and a second semiconductor region (2) connected to a second connection conductor (6), wherein a rectifying junction is present between the two semiconductor regions (1, 2) having opposite conductivity types. Such a device is—after a rotation through 90 degrees—suitable for surface mounting. However, in particular at high voltage and/or high power levels, the diode may suffer from breakdown or a high leakage current.

Abstract: A dual-mode modular pulse-width-modulator capable of outputting low-speed and high-speed control signals is presented. In one mode, a control signal is generated based on timing parametric data stored in a memory. In a second mode, a control signal is generated based on timing parametric data stored in a memory and an external input. Timing parametrics and control variables used to determine the operational mode can be pre-loaded in the memory or loaded through a communication link.

Abstract: A signal processing device contains a plurality of processing elements with inputs and outputs coupled via a switch-matrix for communication of signal streams between a set of processes. An arbiter selects the connections made by the switch-matrix. The arbiter makes allocations of inputs and outputs that are to be connected to each other in each of successive time-slots. The allocations for communication of signal streams between the set of processes for a plurality of time-slots are made in advance. The arbiter can also receive requests for making further connections between inputs and outputs. In that case, the arbiter makes said further connection in a time-slot in which the requested inputs and outputs are not used by the set of processes. A method of planning is provided which ensures that full utilization of the switch-matrix is possible.

Abstract: An electronic circuit having first (VSS) and second (VDD) power supply terminals and comprising a first digital driver (DRV) and a further digital driver (DRVF). The digital drivers (DRV, DRVF) are arranged for driving capacitive loads such as charge pump capacitors (CP1, CP2) of a charge pump (CHGP). The first digital driver (DRV) comprises a first field effect transistor (T1) having a source coupled to the first power supply terminal (VSS), a drain coupled for driving the first charge pump capacitor (CP1), and a gate; a second field effect transistor (T2) having a source coupled to the second power supply terminal (VDD), a drain coupled to the drain of the first field effect transistor (T1), and a gate; a first capacitor (C1) coupled between the gate of the first field effect transistor (T1) and an input terminal (CLK) for receiving a digital input signal (UCLK); and a second capacitor (C2) coupled between the gate of the second field effect transistor (T2) and the input terminal (CLK).