Abstract: A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifier transistor to obtain a conduction angle of at least about 180°. The dc bias circuit includes a self-bias boosting circuit for initially decreasing and then increasing the dc bias voltage provided to a control terminal of the amplifying transistor by the dc bias circuit as the input signal provided to the power amplifier increases. The self-bias boosting circuit is extremely simple and compact in design, and permits the power amplifier circuits to operate in Class B or Class AB with improved power output characteristics.

Abstract: A track and hold amplifier for use in analog/digital-converters comprises, in succession, an input buffer, a pn-junction switch and hold a capacitor. A feedback is provided between the hold capacitor and the input buffer and a second pn-junction switch is provided to disable the feedback during the hold mode.

Abstract: The power consumption of a frequency-divider can effectively be reduced when the frequency of the input signal varies by more than the division factor of a divider cell in the frequency divider. A low frequency input signal requires a lower division factor, and a divider cell in the frequency divider can be bypassed and switched off to obtain this lower division factor, thereby reducing the power consumption.

Abstract: In a waveform generator, a repetitive non-linear waveform is generated by varying the number supplied to a pulse reduction circuit during the repetition period. Consequently, the pulse reduction circuit supplies a number of desired output pulses, which number varies in time corresponding to the varying number. For example, when a lower number is inputted to the pulse reduction circuit during a sub-period of the repetition period, a corresponding lower number of output pulses will be generated. Consequently, a lower number of increment values will be summed or integrated during this sub-period and the waveform changes less steeply.

Abstract: DC/DC conversion circuit (1), includes a transformer (2) having a primary winding (3), a secondary winding (4), and an auxiliary winding (5); a switching transistor (T), including a series circuit with the primary winding (3) between first and second direct current input terminals (6; 7); a start circuit (R1, C1) connected to a control electrode of the switching transistor (T) for switching the switching transistor (T) on by powering the direct current input terminals (6; 7); a control transistor connected to the control electrode of the switching transistor (T) for switching off the switching transistor (T) in dependence on a current flowing through the series circuit during operation.

Abstract: A reset module operates in conjunction with a system clock module to provide a combination of reset and clock assertions that can be relied upon to reset conventional processing modules having a variety of reset architectures. A reset command initiates an assertion of the reset signal and an activation of all clocks at the system level. After a predetermined number of clock cycles, the system level clocks are deactivated, and then the reset signal is de-asserted. By providing multiple clock cycles with the reset signal asserted, processing modules having either asynchronous and synchronous reset will be reset. By disabling the clocks before de-asserting the reset signal, the likelihood of a timing hazard caused by an interaction of the reset signal and a clocking signal is reduced or eliminated.

Abstract: Circuit for generating an inverse signal of a digital signal with minimal delay difference between the inverse signal and the digital signal. Two inverter circuits (6, 8; 7, 9) have been connected in series. The output signal of the second inverter circuit (7, 9) is the digital signal. An input signal for the first inverter circuit (6, 8) is supplied to a pass-through circuit (13, 14) with threshold action. The signal present between the first (6, 8) and the second (7, 9) inverter circuit is supplied to a control input (16) of the pass-through circuit with threshold action. The signal which is also present between the first (6, 8) and the second (7, 9) inverters appears with some delay at the output (17) of the pass-through circuit with threshold action, which signal is the inverse of the digital signal and at the same time constitutes the output signal of the pass through circuit (13, 14) with threshold action.

Abstract: The invention relates to a method of energizing a polyphase motor by means of a plurality of coils (E1, E2, E3), each coil intended to be excited by means of a control signal (I1, I2, I3). The method in accordance with the invention comprises the following steps: identifying the control signal having the largest absolute value, and connecting the corresponding coil to a reference-potential terminal (VCC or GND). The invention enables the losses caused by switching operations in the power stages energizing the coils to be reduced, and to increase the efficiency of the power supply device of the motor.

Abstract: A push-pull amplifier has a level shift circuit to generate different control signals to a driver of a switch. The amplifier has to cope with the voltage limitations of the device. To reduce stand by power the level shifter is used. The solution of the invention has as one of its advantages that a current will flow only during transitions.

Abstract: An integrated circuit (6) has a semiconductor die (47) and an integrated circuit configuration (16) realized on the semiconductor die (47) and situated within bounding faces (52, 53, 54, 55) of the semiconductor die (47), in which two conductor track sections (34, 35) have been provided, which issue from the integrated circuit configuration (16) and which each extend up to a bounding face (55) and which are required for the application of a useful signal (BR1) utilized for test purposes during the fabrication of the integrated circuit (6), and in which an additional conductor track section (41) has been provided, which is disposed adjacent the two conductor track sections (34, 35) and which issues from the integrated circuit configuration (16) and extends toward a bounding surface (55) and preferably up to this bounding face (55) and which serves for the application of a spurious signal (BR2) which interferes with testing.

Abstract: An improved method and structure for a transistor device with a lateral drift region and a conducting top field plate is presented. The method consists of decreasing the gate to drain capacitance by means of decreasing the portion of the field plate that is connected to the gate electrode, and hence the effective overlap of the gate with the drift region and drain. This results in decreased energy dissipation in switching the transistor, and more efficient operation. The rate of decrease of the gate to drain capacitance is even faster at higher drain voltages, inuring in significant energy efficiencies in high voltage applications.

Abstract: In the natural production of human speech, the instant of closure of the vocal cords occurs usually at well defined instants. These instants are used for speech processing, such as glottal synchronous processing or speech synthesis with observed natural vocal cord excitation signals. To detect the instants of glottal closure from an observed speech signal, the observed speech signal is high pass filtered, and a temporally localized aggregate of the number and amplitudes of peaks in the high pass filtered signal is determined for possible instants of glottal closure. The instants of glottal closure are determined as instants where the aggregate takes maximal values.

Abstract: A fully differential, variable gain amplifier comprising an input, an intermediate stage and an output stage, the input stage (100) being coupled to the intermediate stage (200) and the intermediate stage being coupled to the output stage (300). The input stage comprises an amplifier with local feedback means and voltage-to-current conversion means. The intermediate stage has nodes that are shared by the input stage, the output stage and the intermediate stage, respectively, which are connected to the reference node via a relatively low impedance branch. The intermediate stage further comprises current controlled networks coupled to the common nodes via a first feedback branches and branches to the input stage via second feedback branches. The amplifier has means for controlling the gain and the bandwidth independently of one another.

Abstract: Magnetic field sensors and magnetic memories have at least two magnetoresistive bridge elements (A,B,C,D), wherein each magnetoresistive element comprises a free (F) and a pinned (P) ferromagnetic layer. The magnetization directions of pinned ferromagnetic layers are different for the two bridge elements. In the method, in a first deposition step, a first ferromagnetic layer of one of the two said elements is deposited, during which deposition a magnetic field is applied to pin the magnetization direction MP in the first ferromagnetic layer in a first direction. Then, in a second deposition step, a second ferromagnetic layer of the other of the two said elements is deposited, during which deposition a magnetic field is applied to pin the magnetization direction in the second ferromagnetic layer in a second direction different from, preferably opposite to, the magnetization direction in the first ferromagnetic layer.

Abstract: The invention describes a filter arrangement as well as an electronic component, each with a bulk acoustic wave resonator unit which is present on a carrier substrate (1). A reflection element (2) is provided between the carrier substrate (1) and the bulk acoustic wave resonator unit for the purpose of acoustic insulation of the generated oscillations. This reflection element (2) may consist either of several layers of alternately high and low impedance or, if the acoustically reflecting substance has a sufficiently low impedance, of a single layer. In addition, a mobile telephone device, a transmitter, a receiver, and a wireless data transmission system as well as a method of manufacturing an electronic component are described.

Abstract: A semiconductor body (10) has first and second opposed major surfaces (10a and 10b), with a first region (11) of one conductivity type and a plurality of body regions (32) of the opposite conductivity type each forming a pn junction with the first region (11). A plurality of source regions (33) meet the first major surface (10a ) and are each associated with a corresponding body region (32) such that a conduction channel accommodating portion (33a) is defined between each source region (33) and the corresponding body region (32). An insulated gate structure (30,31) adjoins each conduction channel area (33a) for controlling formation of a conduction channel in the conduction channel areas to control majority charge carrier flow from the source regions (33) through the first region (11) to a further region (14) adjoining the second major surface (10b).

Abstract: This transmission system includes at least one transmitter station (8) for transmitting data blocks and at least a satellite station (1) receiving the blocks. The satellite station cuts off the power supply of certain of its circuits when a block does not relate to the satellite station.

Abstract: The invention relates to a so-called punch-through diode with a mesa (12) comprising, in succession, a first (1), a second (2) and a third (3) semiconductor region (1) of, respectively, a first, a second and the first conductivity type, which punch-through diode is provided with two connection conductors (5, 6). During operation of said diode, a voltage is applied such that the second semiconductor region (2) is fully depleted. A drawback of the known punch-through diode resides in that the current flow is too large at lower voltages. In a punch-through diode according to the invention, a part (2A, 2B) of the second semiconductor region (2), which, viewed in projection, borders on the edge of the mesa (12), is provided with a larger flux of doping atoms of the second conductivity type than the remainder (2A) of the second semiconductor region (2).

Abstract: An integrated circuit comprising a substrate with analog and digital sub-circuits provided with different supply terminals, including Vdd and Vss supply terminals for the analog part and a Vdd supply terminal for the digital part, as well as a common substrate terminal or ground terminal. In the substrate, an element with diode function is formed between the Vdd and Vss supply terminals of an analog sub-circuit, which element with diode function comprises a cathode part connected to the Vdd supply terminal and an anode part connected to the Vss supply terminal of the relevant analog sub-circuit. The supply terminals are further connected to the substrate terminal or ground terminal via over-voltage protection circuits, said over-voltage protection circuits for the relevant analog sub-circuit being embodied so as to be active only for positive over-voltages on a supply terminal with respect to the substrate.

Abstract: A simple and cheap dynamic S-correction circuit compensates the higher order errors like the so-called moustache effect and the inner linearity distortion. This is achieved in a known way by connecting an additional proper tuned S-capacitor in parallel with the original one during the start and end of the scan interval. Duty cycle modulation of the on/off times as a function of the frame compensates the inner-pin distortion (also called inner-linearity or modulated S-correction). The duty cycle or the switch on and off instants required to compensate the horizontal distortion or moustache effect is derived by comparing the AC parabolic waveform generated on the S-capacitors with a DC-voltage. Duty-cycle modulation required for compensation of the inner-pin distortion is, in this way, automatically obtained.