Patents Represented by Attorney, Agent or Law Firm Steven R. Biren
  • Patent number: 6456163
    Abstract: A high-frequency amplifier circuit includes an amplifying transistor and a bias circuit directly connected to said amplifying transistor. The bias circuit includes a bias transistor having a control terminal and an inductor coupled to the control terminal, and the bias transistor also has an output terminal directly connected to the amplifying transistor. A resistor is connected in series with the inductor, and the series-connected components are connected in the circuit between the control terminal and a power supply terminal. By providing an inductor in the amplifier in this manner, loading effects on the amplifying transistor at high frequencies is substantially reduced.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: September 24, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Sifen Luo, Tirdad Sowlati
  • Patent number: 6452272
    Abstract: A semiconductor device 1 comprises a body 2 of insulating material having a surface 3 to which a semiconductor element 4 and an interconnect structure 5 are fastened, which interconnect structure 5 is disposed between the semiconductor element 4 and the body 2 of insulating material and has a patterned metal layer 7 facing the body 2 of insulating material, which patterned metal layer 7 comprises conductor tracks 8 and 9. In order to reduce the power consumption of the semiconductor device 1, an insulating layer 12 having a dielectric constant ∈r below 3 is disposed between the patterned metal layer 7 of the interconnect structure 5 and the body 2 of insulating material, and an insulating barrier layer 13 is disposed between the semiconductor element 4 and the insulating layer 12 having a dielectric constant ∈r below 3, so as to counteract that contaminants from the insulating layer 12 having a dielectric constant ∈r below 3 can reach the semiconductor element 4.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: September 17, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Henricus Godefridus Rafael Maas, Maria Henrica Wilhelmina Antonia Van Deurzen
  • Patent number: 6448592
    Abstract: It is known in charge coupled devices to use a dual layer of silicon oxide and silicon nitride as the gate dielectric. Since silicon nitride is practically impermeable to hydrogen, the nitride layer is usually provided with openings through which hydrogen can penetrate up to the surface of the silicon body during the annealing step carried out for passivating the surface. The openings in the nitride layer are provided by a known method, with gates in a first poly layer serving as a mask, in that the nitride is removed from between these gates and an oxidation step is subsequently carried out. According to the invention, the openings in the nitride layer are formed by means of a separate mask (20), such that the edges of the openings (9) in the nitride layer (8) lie at some distance from the edges of the gates.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: September 10, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Hermanus L. Peek, Daniel W. E. Verbugt
  • Patent number: 6448695
    Abstract: A bulk acoustic wave device has a number of resonator elements (14) which are laterally spaced such that a signal (26) applied between to one resonator element (141) at a resonant frequency of the device is coupled to the other resonator elements (142, 143, 144) by acoustic coupling between piezoelectric layers of the resonator elements (14). There are two outer resonator elements (141, 145) and at least one inner resonator element (142, 143, 144). The terminals of the inner resonator elements are electrically connected together. This connection provides an AC short which eliminates the effect of the parasitic capacitances of the inner resonator elements, and provides electromagnetic shielding between the input and output of the device, by reducing the parasitic capacitance between the input and output upper electrodes.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: September 10, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Robert F. Milsom
  • Patent number: 6448855
    Abstract: A power amplifier circuit for amplifying an input signal includes an amplifying transistor and a power detection circuit. The power detection circuit includes a circuit for generating a signal which is directly proportional to the power level in the amplifying transistor. This may-be accomplished by generating a voltage proportional to the square of a current in the amplifying transistor and then averaging that voltage. In this manner, a more accurate indication of the power level in the amplifying transistor is obtained.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: September 10, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Tirdad Sowlati, Sifen Luo
  • Patent number: 6448751
    Abstract: This invention concerns a power supply voltage generator (1) for providing a second supply voltage (VDD2) for an electronic circuitry (60). A voltage converter (50) receives a first supply voltage (VDD1), and converts this into said second supply voltage (VDD2), such that its output voltage (VDD2) fluctuates in a control range between a lower limit (VLOW) and an upper limit (VHIGH). A voltage parameter source circuitry (3) generates a voltage parameter signal (VLOW) which is substantially equal to the minimum supply voltage value (Vmin) of the electronic circuitry (60), and feeds this voltage parameter signal (VLOW) to a parameter input (53) of the converter (50). The voltage parameter source circuitry (3) comprises a VCO (10) incorporated in a PLL. The voltage parameter signal (VLOW) is derived from a control signal (Vcontr) for the VCO (10).
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: September 10, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Rolf Friedrich Philipp Becker
  • Patent number: 6445019
    Abstract: A semiconductor body (11) has first and second opposed major surfaces (11a and 11b). First and second main regions (13 and 14) meet the second major surface (11b) and a voltage-sustaining zone is provided between the first and second regions (13 and 14). The voltage-sustaining zone has a semiconductor region (11) of one conductivity type forming a rectifying junction (J) with a region (15) of the device such that, when the rectifying junction is reverse-biased in one mode of operation, a depletion region extends in the semiconductor region of the voltage-sustaining zone. A number of conductive regions (22) are isolated from and extend through the semiconductor region (11) in a direction transverse to the first and second major surfaces (11a and 11b) so as to be spaced apart in a direction between first and second main regions.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: September 3, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Rob Van Dalen
  • Patent number: 6441454
    Abstract: Inner trenches (11) of a trenched Schottky rectifier (1a; 1b; 1c; 1d) bound a plurality of rectifier areas (43a) where the Schottky electrode (3) forms a Schottky barrier 43 with a drift region (4). A perimeter trench (18) extends around the outer perimeter of the plurality of rectifier areas (43a). These trenches (11, 18) accommodate respective inner field-electrodes (31) and a perimeter field-electrode (38) that are connected to the Schottky electrode (3). The inner field-electrodes (11) are capacitively coupled to the drift region (4) via dielectric material (21) that lines the inner trenches (11). The perimeter field-electrode (38) is capacitively coupled across dielectric material (28) on the inside wall (18a) of the perimeter trench 18, without acting on any outside wall (18b). Furthermore, the inner and perimeter trenches (11, 18) are closely spaced and the intermediate areas (4a, 4b) of the drift region (4) are lowly doped.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: August 27, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Erwin A. Hijzen, Raymond J. E. Hueting
  • Patent number: 6436785
    Abstract: A semiconductor device with a tunnel diode comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types having high enough doping concentrations to provide a tunneling junction. Portions (2A, 3A) of the semiconductor regions adjoining the junction comprise a mixed crystal of silicon and germanium. The doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions. The tunneling efficiency is substantially improved, and also because of the reduced bandgap of said portions (2A, 3A). A much steeper current-voltage characteristic both in the forward and in the reverse direction is achieved. Thus, the tunneling pn junction can be used as a transition between two conventional diodes which are stacked one on the other and formed in a single epitaxial growing process. The doping concentration may be 6×1019 or even more than 1020 at/cm3.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: August 20, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Adam R. Brown, Godefridus A. M. Hurkx, Wiebe B. De Boer, Jan W. Slotboom
  • Patent number: 6438026
    Abstract: A magnetic field element provided with a stack of a first magnetic layer structure (7), a second magnetic layer structure (11) having a substantially fixed direction of magnetization (M11), and a spacer layer structure (9) separating the first magnetic layer structure and the second magnetic layer structure from each other. The magnetic field element is further provided with a biasing means for applying a longitudinal bias field to the first magnetic layer structure, which biasing means includes a thin biasing magnetic layer structure (3) located opposite to the first magnetic layer structure. The biasing magnetic layer structure provides a magnetic coupling field component (M3) perpendicular to the direction of magnetization of the second magnetic layer structure and is separated from the first magnetic layer structure by a non-magnetic layer structure (5). The first magnetic layer structure is ferromagnetically coupled to the biasing magnet layer structure.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: August 20, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Murray Fulton Gillies, Antonius Emilius Theodorus Kuiper, Kars-Michiel Hubert Lenssen
  • Patent number: 6437420
    Abstract: The invention relates to a semiconductor device (100) with a semiconductor body (10) comprising at least one semiconductor element (H) with an active area (A) and a coil (20) coupled to said element (H). The coil (20) and a further coil (21) jointly form a transformer (F). The semiconductor body (10) is secured to a carrier plate (30) which comprises an electrically insulating material and is covered with a conductor track (21). According to the invention, the further coil (21) is positioned on the carrier plate (30) and is formed by the conductor track (21) and electrically separated from the coil (20). In this way, a-device (100) is obtained which is easier to manufacture than the known device. Moreover, the communication between the element (H) and the outside world does not involve an electrical coupling and hence, for example, bonding wires, are not necessary. The invention is particularly advantageous for a (discrete) bipolar transistor, which can suitably be used for surface mounting.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: August 20, 2002
    Assignee: Koninklijke Philips Electronics N. V.
    Inventors: Freerk Van Rijs, Ronald Dekker
  • Patent number: 6438568
    Abstract: The device for converting series of input data elements to series of output data elements is provided with a memory (110) for containing the series of input and output data elements. This memory (110) is embodied so as to successively read a series of input data elements and write a series of output data elements during a single clock cycle.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: August 20, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Marco J. G. Bekooij, Paulus W. F. Gruijters
  • Patent number: 6436779
    Abstract: A semiconductor device has first and second opposed major surfaces (10a and 10b). A semiconductor first region (11) is provided between second (12 or 120) and third (14) regions such that the second region (12 or 120) forms a rectifying junction (13 or 130) with the first region (11) and separates the first region (11) from the first major surface (10a) while the third region (14) separates the first region (11) from the second major surface (10b). A plurality of semi-insulating or resistive paths (21) are dispersed within the first region (1′) such that each path extends through the first region from the second to the third region. In use of the device when a reverse biasing voltage is applied across the rectifying junction (13 or 130) an electrical potential distribution is generated along the resistive paths (21) which causes a depletion region in the first region (11) to extend through the first region (11) to the third region (14) to increase the reverse breakdown voltage of the device.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: August 20, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Godefridus A. M. Hurkx, Rob Van Dalen
  • Patent number: 6424028
    Abstract: A semiconductor device, e.g. power transistor (1, FIG. 1), has a gate or other electrode (4) connected via a test pad (15B) to a set of parallel fingers (21A-21F) in a first portion of a bond pad (12). An ESD protection device (13) is connected via a test pad (15C) to a set of parallel fingers (22A-22C) in a second portion of the bond pad (12). A voltage clamping protection device (14) is connected via a test pad (15A) to a set of parallel fingers (23A-23C) in a third portion of the bond pad (12). The three sets of fingers overlap in an interdigitated pattern defining a bond pad area (24). The transistor (1) and the protection devices (13, 14) may be independently tested and then connected to a same terminal (7C) by a wire (16) bonded over a rectangular bonded region (25) extending across the bond pad area (24). This arrangement allows for a large misalignment in the bond process while still achieving connection of the three bond pad portions.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: July 23, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Harvey F. Dickinson
  • Patent number: 6421752
    Abstract: An electronic apparatus uses a bus conductor driven by wired logic to arbitrate between stations. When arbitration is decided, the apparatus switches to a higher speed mode by supplying additional current to the bus conductor, so that the winning station pulls the potential on the bus conductor against a greater current and the potential rises faster when the station stops pulling the potential.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: July 16, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Herman Schutte
  • Patent number: 6420755
    Abstract: A field effect transistor (T) of the (quasi-)vertical type, which means that in the semiconductor body (10) of the transistor (T), a source (1) and a drain (3) are positioned (approximately) above each other and are separated from each other by the channel region (2), which is connected to a gate region (4), each one of said regions being connected to a connection conductor (6, 7, 11) joining a connection region (7, 8, 12). The connection regions (7, 8) of the source (1) and the gate (4) are situated on top of the semiconductor body (10). The semiconductor body (10) is provided with a through-hole (9) at least one wall of which is covered with a conductive layer (11), which is connected to the drain (3), and which forms the connection conductor (11) of the drain (3) and which is connected to the connection region (12) for the drain (3) situated on top of the semiconductor body (10). In this way, the transistor (T) is very well suited for surface mounting and is also very easy to manufacture.
    Type: Grant
    Filed: November 10, 2000
    Date of Patent: July 16, 2002
    Assignee: Koninklikje Philips Electronics N.V.
    Inventors: Johannes Bloos, Antonius Waltherus Jacobus Petrus Den Boer, Erik Cornelis Egbertus Van Grunsven, Jacob Klerk, Marc Andre De Samber, Johannus Wilhelmus Weekamp
  • Patent number: 6421256
    Abstract: A method for reducing harmonic distortions and switching losses in a power factor correction circuit of a quasi-resonant voltage converter, wherein using data derived from the sensing a voltage impressed on the switching device in the power converter, a multitude of event times can be calculated that will align the timings of the drive circuitry of the power converter to those of the natural resonance transitions of reactive elements of the converter. An over-sampling of the voltage impressed on the switching device voltage allows accurate sensing of a “zero-current” cross-over condition in an inductance of the converter.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: July 16, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Demetri Giannopoulos, Qiong Li
  • Patent number: 6418388
    Abstract: Offset compensation of two orthogonal sensor signals, which are supplied by two sensors and are preferably designed for angle measurements, occurs in dependence on the geometric arrangement of three pairs of test values of the sensor signals in a system of coordinates, the center of a circle on which the three pairs of test values are situated in the system of coordinates having center coordinates &Dgr;x and &Dgr;y relative to the origin of the system of coordinates, correction means are provided which perform a sign determination of the values &Dgr;x and &Dgr;y of the center coordinates of the circle in a repetitive cycle in each measuring cycle, while in each measuring cycle at least one of the pairs of test values differs from the pair of test values used in the preceding measuring cycle, and which means generate correction signals with which the sensor signals are complemented.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: July 9, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Klaus Dietmayer
  • Patent number: 6417526
    Abstract: The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: July 9, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Adam R. Brown, Godefridus A. M. Hurkx, Michael S. Peter, Hendrik G. A. Huizing, Wiebe B. De Boer
  • Patent number: 6418349
    Abstract: An arrangement and a method are described for the transmission of address, instruction and/or data telegrams from a control unit to (at least) one controlled unit and for the return of a respective reception acknowledge signal from the controlled unit (units) to the control unit in response to each address, instruction and/or data telegram, the reception acknowledge signal signaling the control unit the correct transmission of the relevant address, instruction and/or data telegram.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: July 9, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Friedrich Hahn, Gerd Schippmann, Volker Meyer, Kirsten Ohl