Abstract: An amplifier for use in a mobile phone for supplying a signal (Io) to a load (ZL) comprises a first transistor (T1) having a first main terminal coupled to a reference terminal (GND), a control terminal, and a second main terminal for supplying the signal (Io) to the load (ZL), and sensing means for determining the value of the signal (I0). The sensing means comprises a second transistor (T2) having a first main terminal coupled to the first main terminal of the first transistor (T1), a control terminal coupled to the control terminal of the first transistor (T1), and a second main terminal for supplying a further signal (IF) which is a representation of the signal (Io). The amplifier comprises detection means (DMNS) for supplying a DC-component (IDC2) of the further signal (IF).

Abstract: An arrangement for generating an error signal representing the differences between an input signal voltage level (xpk, xnk) and an estimated value (rp, rn) for the input signal voltage level comprises first (T1, T2) and second (T5, T6) transconductors and a differencing circuit (T3, T4, T7, T8) which forms the modulus of the difference between the outputs of the transconductors. The error signal is converted into a probability signal by subtracting the error signal from a constant signal (408) to produce a signal at the output (407) which is a maximum when the input voltage level and estimated voltage level are equal.

Abstract: In a trench-gate semiconductor device, for example a cellular power MOSFET, the gate (11) is present in a trench (20) that extends through the channel-accommodating region (15) of the device. An underlying body portion (16) that carries a high voltage in an off state of the device is present adjacent to a side wall of a lower part (20b) of the trench (20). Instead of being a single high-resistivity region, this body portion (16) comprises first regions (61) of a first conductivity type interposed with second regions (62) of the opposite second conductivity type. In the conducting state of the device, the first regions (61) provide parallel current paths through the thick body portion (16), from the conduction channel (12) in the channel-accommodating region (15). In an off-state of the device, the body portion (16) carries a depletion layer (50).

Abstract: In a method of generating red, green and blue color signals, the red, green and blue color signals are picked up by red, green and blue color sensors each having a horizontal read-out register, while first n-phase clock signals (&phgr;C1, &phgr;C2, &phgr;C3), generated (DEL) from a pixel clock signal (f), are processed (MUX-G) to obtain second n-phase clock signals (&phgr;C1(G), &phgr;C2(G), &phgr;C3(G)) for the read-out register of the green color sensor in order to obtain an electronic half pixel offset for the green color signal with respect to the red and blue color signals.

Abstract: Single panel scrolling color projection systems using three (red, blue and green) scrolling color stripes have been demonstrated to be adequate for television images. However, computer graphics displays are more prone to color artifacts. The invention increases the number of scrolling color stripes in order to suppress these artifacts. One implementation is to break up the three color stripes into multiple bands using a lenticular lens array, and then to collimate the multiple stripes with a second lens array. The collimated stripes are scrolled using the rotating prism of the prior systems.

Abstract: A data bus for serial bus transmission between apparatus which are capable of transmitting and/or receiving data via the data bus, recessive and dominant states being present on the data bus and each state being assigned a respective bit value. In order to interrupt a message of low priority by a message of higher priority without incurring a time delay and without additional channels being required, messages are transmitted in message blocks, each message block having at its beginning a start block with (n+k) dominant and j subsequent recessive bits and subsequent data blocks with n data bits and m subsequent recessive bits. A message block of low priority currently being transmitted can be interrupted by another apparatus in order to transmit a message block of higher priority in that the other apparatus generates a new start block on the data bus and subsequently transmits the associated data blocks.

Abstract: The invention relates to a detector circuit (100) for detecting short-lasting voltage pulses (spikes) in a power supply voltage (VDD). An integrator (INT) forms the average value (VDD_AV) of the power supply voltage (VDD) and a corresponding energy is stored in a first memory (MEM1). A comparator (COMP) compares the power supply voltage (VDD) with a predetermined voltage interval ([Vref1, Vref2]) and closes a switch (S) when the power supply voltage is outside this interval. The energy from the first memory (MEM1) then flows into a second memory (MEM2) via the switch (S) and a delay circuit (DELAY). When the energy in the second memory (MEM2) exceeds a threshold value, an output stage (OUT) is thereby activated, whose output supplies a signal (SPIKE_DET) indicating a voltage spike.

Abstract: The present invention relates to a switched-mode power supply comprising a transformer (T1) having an additional control winding (N2). This control winding (N2) forms part of an over power protection system by providing information relating to the line voltage Vline. Additionally, the control winding (N2) forms part of an over voltage protection system by monitoring the output voltage, Vout, of the switched-mode power supply. The sensing of Vline and the monitoring of Vout is performed in a time phased way so that the same control winding (N2) may be used to provide a plurality of information relating to the performance/status of the switched-mode power supply.

Abstract: An electronic device having a resonance frequency with a margin of error sufficiently small for high frequency applications. The electronic device includes a first capacitor electrode in a first electrically conducting layer, a dielectric including a layer of dielectric material and a distinct electrically insulating material, and a second capacitor electrode in a second electrically conducting layer.

Abstract: The invention proposes an interface circuit having a very low power consumption and generating very low interference noise in the sensitive band of ratio chips. It is advantageously used to interface a microprocessor with a baseband radio processor in a telecommunication device, for example in DECT or GSM phones. The interface of the invention is current-driven. It comprises a current driver for transmitting a current in a transmission line depending on the data to be transferred. It also comprises a current receiver. The current receiver has an input node and an output node interconnected via a current mirror circuit, so that the voltage on said input node is near to the ground voltage and the voltage on said output node is changing depending on the transferred data.

Abstract: Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. The trench-gate (11) is accommodated in a narrow trench (20) that is etched via a narrow window (52b) defined by the spacers (52) at sidewalls of a wider window (51a) of a mask (51) at the body surface (10a). The spacers (52) permit a source region (13) adjacent to the trench-gate (11) and an insulating overlayer (18) over the trench-gate (11) to be self-aligned to this narrow trench (20). The overlayer (18), which defines a contact window (18a) for a source electrode (33), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers (52). Its overlap (y4, y4′) with the body surface (10a) is well-defined, so reducing a short-circuit risk between the source electrode (33) and the trench-gate (11).

Abstract: A semiconductor body has source and drain regions (4 and 5; 4′ and 5′) spaced apart by a body region (6; 6′) and a drain drift region (50; 50′) and both meeting the same surface (3a) of the semiconductor body. An insulated gate structure (7; 70′; 700) is provided within a trench (80; 80′; 80″) extending in the semiconductor body. The gate structure has a gate conductive region (70b; 70′b; 70″b) separated from the trench by a dielectric layer (70a; 70′a) such that a conduction channel accommodation portion (60; 60′) of the body region extends along at least side walls (80a; 80′a; 80″a) of the trench and between the source (4; 4′) and drain drift (50; 50′) regions.

Abstract: The invention provides a write driver circuit for writing an information signal on a magnetic record carrier. The write driver circuit comprises a first and a second input terminal (20,22) for receiving the information signal. A first current sink (24) is available, having a first transistor (T3) of a first type, having a first main electrode coupled to the first point of constant potential (+), having a second main electrode coupled to the first input (34) of a write head combination (32) via a first impedance (38), and a control electrode coupled to the first input terminal (20). A second current sink (28) is available having a second transistor (T4) of the first type, having a first main electrode coupled to the first point of constant potential (+), having a second main electrode coupled to the second input (36) of the write head combination via a second impedance (42), and a control electrode coupled to the second input terminal (22).

Abstract: An arrangement for improving the ESD protection in a CMOS buffer includes a plurality of PMOS transistors (31 to 37) and a plurality of NMOS transistors (41-47) which are connected in series with the PMOS transistors and have a finger width WN which is larger than the finger width WP of the PMOS transistors in order to be capable of withstanding an increased current load in the case of an electrostatic discharge.

Abstract: An electronic device which includes a periodic signal generator (12) and a frequency multiplier circuit (14) for multiplying the frequency of the periodic signal. The multiplier circuit is formed on the basis of an EXCLUSIVE-OR gate (20), which receives the periodic signal, and a frequency divider circuit (22) connected between the output and an input of the gate. From this divider circuit it is possible to derive in a very simple way quadrature signals, which makes it feasible to perform a modulation of the type known as “zero demodulation”. The multiplier circuit can operate in accordance with CML technology (Current Mode Logic).

Abstract: In an electroacoustic transducer (1) having a magnet system (8) and having a diaphragm holder (2) for holding a diaphragm (17) and having a moving coil (115) connected to the diaphragm (17), the moving coil (15) has a hollow cylindrical coil body (27) and two connecting leads (28, 29), a holding element (38, 39) connected to the diaphragm holder (2) being provided for each connecting lead (28, 29), which holding elements (38, 39) are constructed to be elastically deformable in a direction substantially parallel to the diaphragm axis (26) and, preferably, also to be mechanically damping.

Abstract: The manufacture of a vertical power transistor trench-gate semiconductor device in which the source regions (13) are self-aligned to the trench-gate structures (20,17,11) including the steps of forming a mask (61) on a surface (10a) of a semiconductor body (10), using the mask (61) to form the trench-gate structures (20,17,11), then using the mask (61) to form U-shaped section layers (62A, 62B) of insulating material whose base portion (62B) provides a gate insulating layer on the gate material (11), then removing the mask (61) and forming spacers (64) against well-defined steps provided by the upright portions (62A) of the U-shaped section layers, then using the spacers (64) to form the source regions (13).

Abstract: A semiconductor device comprises a semiconductor body (10) in and on which a power transistor (T; 1, 2, 3) and a suppression diode (D; 100) are integrated. A diode junction (40; 40′) is present between the back metallization (22) and the adjacent region (2) of the power transistor so as to provide the diode in series with this region (2) and adjacent to the back surface (12) of the body. This diode junction (40; 40′) opposes the p-n junction (42) between the collector or drain region (2) of the transistor and its base region (3), so as to suppress reverse current flow in the transistor. The higher doped part (2b) of the adjacent transistor region (2) is sufficiently thick as to prevent any minority charge carriers injected by the diode junction (40; 40′) from reaching the p-n junction (42) with the base region (3). The diode junction may be a p-n junction (40) or a Schottky barrier (40′).

Abstract: A sub-net operation with increased availability and reduced power consumption is achieved in a bus system with a plurality of stations (10, 11, 12) which are coupled to one another via a system of conductors (13, 14). Each of the stations includes a transceiver (21) and a control unit (30). The stations are switched from a quiescent state to a standby state in response to the reception of a first wake-up signal and selected stations are switched to a normal operating state upon reception of a second wake-up signal, whereby stations are selected.

Abstract: For an optimal adjustment of the filter frequency of a signal filter, independently of external influences, process spreads and temperature fluctuations, a filter circuit for filtering at least one sound carrier in a composite video signal by at least one signal filter (24) having at least one filter frequency which is adjustable in dependence upon a control signal, is characterized in that the filter circuit (1) includes a reference filter (11) whose filter frequency is adjustable in dependence upon the control signal and which shifts the phase of a reference signal applied thereto by a defined value when tuning the filter frequency to the frequency of said reference signal, in that a phase comparator (14) is provided which receives the output signal of the reference filter (11) and the reference signal, in that the control signal is derived from the output signal of the phase comparator (14) in such a way that the reference filter (11) is tuned to the frequency of the reference signal, and in that an output