Abstract: A high-voltage capacitive voltage divider circuit includes a high-voltage Silicon-On-Insulator (SOI) capacitor connected between a high-voltage terminal and a low-voltage terminal, and a low-voltage SOI capacitor connected between the low-voltage terminal and a common terminal. The voltage divider circuit also includes control circuitry for processing a signal generated at the low-voltage terminal in order to provide voltage-related control of a larger circuit employing the voltage divider circuit. The high-voltage SOI capacitor can include an oxide layer on a substrate, with a thinned drift region on the oxide layer, a thick oxide layer over the thinned drift region, and an electrode layer over the thick oxide layer, with the electrode layer and the thinned drift region forming capacitor plates insulated from each other by the thick oxide layer.

Abstract: The manufacture of a trench-gate semiconductor device, for example a power transistor or a memory device includes the steps of forming at a surface (10a) of a semiconductor body (10) a first mask (51) having a first window (51a), providing a thin layer of a second material (52) in the first window (51a), forming an intermediate mask (53A, 53B) of a third material having curved sidewalls and using the intermediate mask (53A, 53B) to form two L-shaped parts (52A, 52D and 52B, 52E) of the second material with a second window (52a) which is used to etch a trench-gate trench (20). The rectangular base portion (52D, 52E) of each L-shaped part ensures that the trench (20) is maintained narrow during etching. Narrow trenches are advantageous for low specific on-resistance and low RC delay in low voltage cellular trench-gate power transistors.

Abstract: The invention relates to a push-pull amplifier comprising a logic circuit for supplying control signals to the power switches comprising a carrousel part and a handshake part. In this way, it can be prevented that both switches can be closed at the same time.

Abstract: A method for increasing the maximum useable supply voltage in an amplifier circuit is presented. A self-biased cascode amplifier circuit includes a first MOSFET and a second MOSFET connected in series and coupled between a DC voltage source terminal and a common terminal. An RF input signal terminal is coupled to a gate electrode of the first MOSFET, and the gate of the second MOSFET is connected between a resistor and a capacitor connected in series between the drain of the second MOSFET and the source of the first MOSFET. In preferred embodiments a unidirectionally-conducting boosting sub-circuit is coupled between a drain electrode and the gate electrode of the second MOSFET, which may comprise a diode-resistive sub-circuit, or a third MOSFET connected across a resistive voltage divider. The output of the amplifier circuit is taken from the drain electrode of the second MOSFET.

Abstract: A semiconductor device comprises one or more field effect devices (FD) having source and drain regions (5 and 6) spaced apart by a body region (3a). A gate structure (7a, 7b), preferably in a trench (4), controls a conduction channel in a portion (3b) of the body region (3a) between the source and drain regions. The device has one or more mesa structures (100) having end and side walls (100a to 100d). The body region (3a) extends between and meets at least the side walls (100c and 100d) of the mesa structure. The gate structure (7a, 7b) extends along and between the side walls such that the conduction channel accommodating portion (3b) extends along and between the side walls (100c and 100d). The source and drain regions (5 and 6) meet respective end walls (100a and 100b) of the mesa structure and/or its side walls (100c and 100d). At the mesa walls, a source electrode (S) contacts the source region (5) and a drain electrode (D) contacts the drain region (6). (FIGS.

Abstract: An insulated-gate field-effect semiconductor device, preferably of the SOI type, has source (3) and drain (4) regions in a semiconductor body portion (1) at a first major surface of a semiconductor substrate (10). The gate-terminal metallisation (25) is present at an opposite second major surface (12) of the substrate (10). A gate connection (15,55) is present between the gate electrode (5) and the substrate (10) to connect the gate electrode (5) to the gate-terminal metallisation (25). This arrangement permits better use of the layout area for source-terminal and drain-terminal metallisations, and their connections, at the upper major surface (11) of the body portion (1), without introducing an on-resistance penalty. The part of the gate connection provided by the substrate (10) does not increase the on-resistance of the main current path through the device, i.e. between the source (3) and drain (4).

Abstract: In a trench-gate field-effect transistor of inverted configuration, the drain region (14) is adjacent to the surface with the insulated trench-gate structure (11,12). The gate dielectric 12 is thicker adjacent to the drain region (14), and preferably also the drain drift region (14a), than it is adjacent to the channel-accommodating portion (15a) of the transistor body region (15). Another portion (15b) of the transistor body region (15) is electrically shorted to the underlying source region (13) by a buried electrical short (35). This buried short is provided by a leaky p-n junction (35) between a highly doped (p+) bottom portion (15b) of the body region and the underlying source region (13), at an area that is separated laterally from the insulated gate electrode (11) by an active portion (13a) of the source region adjacent to the gate trench (20). This portion (13a) of the source region can be formed by dopant implantation and/or diffusion via the lower portion of the trench (20).

Abstract: A switch mode power supply (SMPS) and method are provided. In particular, the present invention provides an SMPS in which data is encoded by manipulating voltage pulses on a primary side. The manipulated voltage pulses are then transferred over a transformer to a secondary side. Secondary side pulses generated in response to the primary side pulses are sensed and decoded by a detector. The present invention allows data to be transferred from the primary side to the secondary side without affecting output voltages.

Abstract: In an integrated circuit (IC) for providing an enabling signal (EN) to a converter, the integrated circuit (IC) includes a monitoring circuit (FET1, R2, D1, Io, M, S1) for providing a control signal (CS) in response to a level of a line voltage (Vline) on a first connection terminal (8) of the integrated circuit (IC), and a start-up circuit (FET2, Istrt_up, Vcc_strt-Lev, COMP, S2) for providing the enabling signal (EN) to the converter in response to the control signal (CS) and a generated voltage level (Vcc), the generated voltage level (Vcc) being generated in response to the level of the line voltage (Vline) on the first connection terminal (8). The monitoring circuit and the start-up circuit sense the level of the line voltage (Vline) only via the first connection terminal (8).

Abstract: An electroacoustic transducer (1) has a magnet system (7) and a moving coil (15), which is disposed in the air gap (14) of the magnet system (7), and a diaphragm (17) attached to the moving coil (15). The diaphragm (17) has a mounting zone (24) for mounting the moving coil (15), and projections (25) in the mounting zone (24). The diaphragm (17) also has an interspace between every two projections (25), and two stabilizing walls (32, 33), which are inclined with respect to the diaphragm axis (18), are arranged in each interspace and are arranged so as to form a roof shape and are formed so as to project beyond the mounting zone (24) in radial directions.

Abstract: The invention relates to the manufacture of semiconductor elements (10), in which manufacturing process a part (50) of a semiconductor body (11) having a silicon substrate (32) from which the semiconductor elements (10) are formed is removed by means of powder blasting. For this purpose, the surface of the semiconductor body (11) is provided with a mask pattern (40). In this manner, for example, discrete diodes (10) are manufactured in a simple and inexpensive way. A drawback of the known method resides in that it results in diodes (10) having non-uniform properties which, in addition, cannot be readily reproduced from batch to batch.

Abstract: The forward and reverse blocking voltage capability of a thyristor in accordance with the invention is substantially independent of the active thyristor area (Aa), thereby facilitating its design and its manufacture. This is achieved by means of a concentric arrangement of a deep inner lower-doped perimeter zone (42) of the forward base region (2) with a deep outer perimeter zone (43) of the same conductivity type, doping profile and depth (A4xj=Axj). The outer perimeter zone (43) brings the reverse blocking p-n junction (34) to the front surface (11) at a lateral distance (D3) around the forward blocking p-n junction (32). The outer perimeter zone (43) extends in depth to a lower perimeter zone (44) of the underlying region (4) that forms the reverse blocking junction with the high-resistivity base region (3) of opposite conductivity type. All these perimeter zones (42-44) together provide the thyristor with a deep peripheral termination which surrounds the active thyristor area (Aa).

Abstract: A method of manufacturing a semiconductor device in which a semiconductor element, such as a diode, is attached to a support plate and provided with a plastic encapsulation. The plate is provided with a flange which is provided with an undercut region in order to improve the connection between the plate and the encapsulation. The plate is made from a ductile material. A step is formed in the surface of the plate by pressing using a first die, and by pressing using a second die, the flange provided with the undercut region is formed at, or near, the wall of the step. The flange should be formed at, or very close to, the wall of the step in the plate.

Abstract: A method and apparatus for providing closed loop feedback control is presented. The method consists of a hybrid software and hardware solution to take advantage of the useful attributes of both. Analog signals output by the device are sampled at a rate sufficient to preserve all necessary high frequency information, and preprocessed at high speed in hardware. The outputs of the preprocessing stage are then operated on in software at much lower speeds. The method and apparatus allow for the complex real time processing of feedback signals in the digital domain, yet allow the cost efficiencies and programming flexibility of a standard micro-controller to be utilized.

Abstract: An image pick-up includes a number of active sensor elements (11; 12; 13; 14) arranged in an array and a number of conductive lines extending over the surface of the array for the transfer of supply and signals. Each sensor element includes a light sensor (20) and an amplifier. According to the invention, a reduction in the number of lines can be achieved while functionality is maintained. In a first and a second embodiment (11; 12), a sensor element includes a first switch (S1) associated with the sensor and a second switch (S2; S3) associated with the amplifier, the switches being controlled by a common control signal. In a third embodiment (13), a sensor element includes a series arrangement of a first switch (S1) and a second switch (S2) included between the sensor and a supply line. In a fourth embodiment (14), a select signal is also used as a supply for the amplifier.

Abstract: In an evaluation circuit for evaluating an output signal of a magnetoresistive sensor (1) for rotational speed measurement, in which the evaluation circuit performs an offset compensation of the sensor signal and comprises a comparator (4) which receives the offset compensated sensor signal and compares it with a reference voltage, a reliable identification of the output signal of the sensor after switching on the arrangement is ensured in that, in an initial mode, the value of the reference voltage is selected in dependence upon the temperature, the temperature dependence being approximated to that of the sensor signal, in that a control unit (6) is provided which, in the initial mode, consecutively checks whether the sensor signal is present, triggers the offset compensation only after the presence of said signal, subsequently checks whether the comparator (4) supplies an output signal, and changes over to a control mode only after the presence of said signal, in which control mode the temperature dependenc

Abstract: A novel magnetic data storage system and a sensing system of magnetic characteristics are disclosed; the systems have a magnetization direction that is irreversible in an external magnetic field. A method of manufacturing, a method of resetting or changing or repairing and a method of operating such systems are also disclosed. The systems can include a set of magnetic devices in a balancing configuration; essentially each of said devices comprises a structure of layers including at least a first ferromagnetic layer and a second ferromagnetic layer with at least a separation layer of a non-magnetic material there between, said structure having at least a magneto resistance effect. The magnetization direction of the first ferromagnetic layer of at least one of said devices is irreversible in an external magnetic field higher than about 35 kA/m.

Abstract: A method is described of manufacturing a semiconductor material having a zone (200) with p-conductivity type and n-conductivity type regions with dopant concentrations and dimensions such that, when the n- and p-conductivity type regions are depleted of free charge carriers the space charge per unit area of the regions balances at least to the extent that the resulting electric field is lower than that at which avalanche breakdown would occur in the area. The method starts with a semiconductor body having adjacent a first major surface (10b) a first semiconductor region (2) of one conductivity type. A mask (3, 4, 5) is provided on the first major surface, having at least one mask area masking a part (2a) of the first region. At least a part of the unmasked first region (2) is then removed to provide at least one opening (7) in the first region.

Abstract: A cascode bootstrapped analog power amplifier circuit includes a first MOSFET and a second MOSFET connected in series and coupled between a dc voltage source terminal and a common terminal. An rf input signal terminal is coupled to a gate electrode of the first MOSFET and a dc control voltage terminal is coupled to a gate electrode of the second MOSFET, with a unidirectionally-conducting element such as a diode-connected MOSFET being coupled between a drain electrode and the gate electrode of the second MOSFET. The output of the amplifier circuit is taken from the drain electrode of the second MOSFET. This circuit configuration, permits he first and second MOSFETs to withstand a larger output voltage swing, thus permitting the use of a higher supply voltage and resulting in a substantially increased maximum output power capability for a given load value.

Abstract: An amplifier has a cascade circuit including an input circuit, a cascode circuit and an output circuit. The input circuit receives input signals via an input (10), which input signals are converted to amplified signals by the cascode circuit. These amplified signals are subsequently supplied to an output (94) by the output circuit. The cascode circuit includes two input transistors (40 and 62) and an output transistor (74). By means of three capacitors (32, 46 and 50) and a coil (48), the cascode circuit is built up in such a way that the input transistors (40 and 62) are parallel-connected for comparatively high-frequency input signals, while the input transistors (40 and 62) are series-connected for comparatively low-frequency supply signals. This results in the transconductance being doubled, while the DC collector current or drain current remains the same.