Abstract: A semiconductor diode includes a semiconductor body having a first region (1) of one conductivity type, a second region (2) of the opposite conductivity type meeting only a given surface (4) of the body and surrounded by the first region (1) so as to form with the first region (1) a first pn junction (3) which, when reverse-biassed in operation of the diode by a voltage applied across the diode, gives the diode a blocking characteristic, and a third region (15) of the one conductivity type more highly doped than the first region (1) provided within the first region (1) for triggering conduction of the diode when a predetermined voltage less than that at which the main pn junction (3) would have broken down in the absence of the third region (15) is applied across the diode to reverse bias the first pn junction. The third region (15) meets only the given surface (4) and a passivating layer (9) on the given surface covers the third region (15).

Abstract: In a memory cell which is connected between two bit lines, information is stored after selection by causing a first bit line to convey a signal which is complementary to that on a second bit line. It is known, starting from a single data supply line which may convey either a high or a low signal, to provide a memory circuit per column with inverting means so as to be able to charge both bit lines complementarily. Here, this complementary charging is done by connecting, upon selection, the first bit line to the data supply line and connecting a transistor with its main electrodes between ground and the second bit line, which transistor receives the data at its control electrode. This transistor then constitutes, with the bit line load, an inverter. Lay-out aspects relate to the common use of substrate area of two adjacent columns and the common use of a contact in the shown circuit arrangement.

Abstract: In CMOS integrated circuits, "latch-up" problems may arise if no special steps are taken. One way to counteract a "latch-up" state is to apply a substrate bias voltage. In an integrated circuit, an externally-clocked substrate bias voltage pump and a stand-by bias voltage generator are provided, the latter not being switched on until the substrate bias voltage becomes less negative than, for example, -2V. As a result, the integrated circuit becomes less sensitive to "latch-up", especially during measuring and testing procedures, in which no external clock signal is supplied.

Abstract: A semiconductor laser having a layer structure including a first and a second passive layer of opposite conductivity types, an active layer therebetween which forms a pn junction with one of the passive layers, and a current-limiting blocking layer which forms a reverse-biased pn junction bounding a radiation emitting active region of the active layer. The active region has a thickness which exceeds that of the remainder of the active layer, and extends through the blocking layer at least as far as the other passive layer. This achieves effective electrical and optical confinement of the active region, enabling a sufficiently low threshold current for laser operation at room temperature.

Abstract: The invention relates to a charge-coupled device with bulk transport (PCCD or BCCD), in which the lateral boundary is formed by zones (6) of the same type as and having a lower concentration than the charge transport channel. The potential barriers necessary for the lateral bounding are induced in these channel-bounding zones via the clock electrodes (7) of the CCD. As compared with conventional CCD's with bulk transport, in which the lateral boundary comprises a cut-off pn junction, a CCD of the type suggested here has the important advantage of low dynamic leakage currents.

Abstract: In conventional digital-to-analog converters one of a number of multi-emitter transistors is driven by means of the select logics, the emitters of which are connected selectively to a group of data lines. The output circuits connected to the data lines further receive a reference voltage to be able to detect the condition on the data lines. In the analog converter according to the invention each data line is constructed so as to be complementary in which the emitters which in the prior art circuit arrangement are connected to the first group of data lines are coupled in the same manner to a first group of data lines while the remaining emitters are now connected to complementary lines from the second group. The output circuits which are connected to the data lines receive a logic signal of a data line and the complementary logic signal of the associated complementary data line. The result is that the voltage step which is presented to the inputs of the output circuits is twice as large.

Abstract: A memory includes a sense amplifier with a buffer (TA) positioned at the end of each bit line, the buffer amplifier being alternatively used as a "sense amplifier". On the bit line Q the buffer amplifier includes only five transistors; the transmission transistor TR ("passing transistor") is activated during the read operation RD, and also during the precharging operation PCH; as a result thereof the output signal S always has zero value during the precharging operation. The parasitic capacitance CS is small relative to the equivalent capacitance CB of the bit line Q, and the supporting inverter SI is small with respect to the amplifying inverter PI.

Abstract: A circuit for a MOS-type integrated device includes two cross-coupled drain-gate transistors. In order to supply filtered voltages V'DD and V'SS which are equivalent to VDD and VSS, an N-channel first transistor has its source connected to VSS and its drain supplies the voltage V'SS, while a P-channel second transistor has its source connected to VDD, and its drain supplies the voltage V'DD. A third transistor may also be provided in order to accelerate the initial switching of the circuit should its state not be appropriate when voltage is applied.

Abstract: A semiconductor device includes a prediffused array of elementary gates which constitute an integrated circuit (designated as a "custom made circuit") realized on gallium arsenide. The elementary gates which constitute the elements of the prediffused array realize OR/NOR functions according to SCFL logic and constitute both internal gates for the "custom made circuit" and external gates compatible with ECL logic to directly connect the circuit thus formed to an external semiconductor device realized according to ECL logic.

Abstract: A current source circuit comprises a first enhancement mode field effect transistor arranged as a current source. A drive voltage which is generated by a second depletion mode field effect transistor and a third depletion mode field effect transistor is applied to the drive electrode of this first transistor. The drive voltage is such that the output current of the first transistor is substantially independent of temperature variations.

Abstract: A circuit for performing operations on two bits (A,B), including the processing of a carry from a preceding circuit (CIN) and transmitting it to a subsequent circuit (COUT). The circuit includes a network which is formed by MOS transistors which can be programmed via programming lines and which supplies a logic combination. An exclusive carry-propagation-generation device is formed by three MOS transistors which are connected in series between a carry-propagation line and ground and whose gates are connected to one of the bits to be processed, to the logic combination, and to a carry inhibit line, respectively.

Abstract: A supply voltage originating from the charge present across a buffer capacitance connected in parallel with a logic gate including CMOS transistors is present across this gate. The loss of charge occurring when the capacitively loaded gate output is charged must be replenished. To this end there is provided a small direct current source feeding the buffer capacitance.

Abstract: By providing an intrinsic semiconductor region in a reverse biased junction cathode between an n-type surface region and a p-type zone, a maximum field is present over the intrinsic region in the operating condition. The efficiency of the cathode is increased because avalanche multiplication can now occur over a greater distance, while in addition electrons to be emitted at a sufficient energy are generated by means of tunneling.

Abstract: A semiconductor device having one or more first non-volatile memory transistors and a detector having a second non-volatile memory transistor with which a charge level written in the first transistor is safeguarded and corrected, if necessary, by a suitable, incorporated bias voltage between source zone and control electrode and/or a margin fixed by an incorporated difference in threshold voltage. A further non-volatile memory transistor may be present with which there is detected, during writing, erasing or rewritting, whether the desired charge level in the first transistor is reached and the charge transport is to be terminated.

Abstract: The invention relates to an active symmetrical balance hybrid circuit. The hybrid circuit includes an input, an output and an in/output as well an impedance circuit per half section connected to the input and output which is connected between the in/output and one or more virtual ground points. Between a virtual ground point and one of the supply lines a signal transistor is inserted. The hybrid circuit further includes per half section two auxiliary transistors connected between the supply lines and the in/output. The auxiliary transistors multiply by the same factor the current flowing through a signal transistor together with which the auxiliary transistor is incorporated in a current mirror circuit. A signal transistor can be incorporated in a current mirror circuit with one or two auxiliary transistors in the same half section, but also by means of a universal coupling of the two half sections both with an auxiliary transistor in the one and an auxiliary transistor in the other half section.

Abstract: An integrated circuit comprising complementary field effect transistors which are both of the normally-off depletion type. These transistors have, in the channel region a surface layer which has the same conductivity type as the adjoining source and drain zones. The surface layers comprise, per unit surface area, a quantity of dopant which is at least equal to the charge per unit surface area in the part of the substrate region which adjoins the surface layer and which is depleted if the threshold voltage is applied between the gate electrode and the source and drain zones. The gate electrodes comprise semiconductor material of opposite conductivity types.

Abstract: A frequency-modulated digital signal demodulator includes a digital quadrature filter having n elements arranged in cascade, each delaying the input signal by a value T.sub.E =1/F.sub.E, where F.sub.E is the sampling frequency, a number of channels arranged in parallel with the cascade arrangement of delay elements, each channel having a multiplier for multiplying by a given coefficient, a first and a second summing circuit for summing the respective output signals of said multipliers, the output signals of the two summing circuits constituting the quadrature output signals of the filter and being referred to as reference and phase-shifted signals. At the output of the filter a circuit for calculating the instantaneous phase .phi..sub.n of successive signal samples is provided.

Abstract: Current flow through the base region of a hot charge-carrier transistor is by hot majority charge-carriers of one conductivity type (i.e., hot electrons for a hot electron transistor) which are injected into the base region at an emitter-base carrier region. In accordance with the invention a low base resistance is achieved by forming the base region as alternate layers of semiconductor material (for example silicon) and metal-based material (for example epitaxial cobalt or nickel silicide) which has a higher conductivity than the semiconductor material. The base-collector barrier is adjoined by a semiconductor layer of the base region, and the (or each) metal-based layer in the vicinity of the emitter-base carrier and/or the base-collector barrier is sufficiently thin (for example about 1nm or less) to permit quantum mechanical tunnelling. This aids efficient transmission of the hot charge-carriers through the base region and over the base-collector barrier.

Abstract: The invention relates to an optoelectronic component for surface mounting of the type having an opto-electronic element arranged on the bottom of a cavity provided in a support and to the method of manufacturing same. The component includes a cavity coated with a metallization coating. The optoelectronic element is soldered on the bottom of the cavity. The support is a substrate of Si strongly doped with the first conductivity type, whose surfaces are orientated according to the plane (100), while the metallized surfaces of the cavity are formed by the preferential attack according to the planes (111). Regions of the second conductivity type are diffused into the cavity and into a cavity merging into the latter from the lower surface of the substrate. The element is soldered with suitable polarity, and insulation is provided by a diode connected with reverse polarity in parallel with its terminals. The contact points at the lower surface of the substrate permit surface mounting.

Abstract: In a radiation-sensitive semiconductor device, for example a quadrant diode, having several rectifying junctions, the mutual distance between these junctions can be considerably reduced by keeping the junctions cut off by means of circuit elements in such manner that associated depletion regions touch each other. Charge carriers generated between two junctions are substantially always collected by the appropriate junction. With this arrangement, low crosstalk and good high-frequency properties can be realized. Furthermore, the semiconductor body in which the rectifying junctions are realized may comprise further circuit elements, which permits integration of the radiation-sensitive semiconductor device with other elements.