Abstract: In relatively large systems of (integrated) circuits, data signals can experience a delay which is in the order of magnitude of a clock-pulse period. The receiving circuit (i.e. receiving the data signal) then receives the data signal too late (the clock pulse has ceased) and can at that moment no longer take over the data signal for further processing or transport. In the system according to the invention the clock pulses are led via a delaying element (for example, the inverting circuits in series) to the receiving circuit (slave of the master/slave flip-flop). The data output of the receiving circuit is connected to a data input of another circuit (master of another master/slave flip-flop), which receives the undelayed clock pulses, the data delay between the receiving circuit and the other circuit being negligible. The data delay is thus distributed over two clock pulses.

Abstract: For the testing of an integrated monolithic circuit (IC) the integrated monolithic circuit with a test bus which extends along a functional part of the circuit which is partitioned into macro circuits and which is coupled to the macro circuits, each macro circuit comprising a test interface circuit which is connected in series with test interface circuits of the other macro circuits; via the test interface circuits, the macro circuits can be coupled to the test bus. As a result, macro circuits can be separately tested and in the case of a hierarchic design of integrated circuits, utilizing previously designed marco circuits and test programs for previously designed macro circuits, test development times can be substantially reduced; this is an increasingly important aspect of increasingly complex circuits.

Abstract: This fast-access data storage circuit is made of a semiconductor material with a two-dimensional carrier gas between two of its layers. The material is rendered superconducting by a suitable choice of the temperature and magnetic field conditions. The circuit is formed by a plurality of memory cells, each of which is formed by two selection transistors, a semiconductor loop, ohmic contacts and a grid which is arranged on the loop and one of the contacts. The superconductivity reduces the access time. One selection controls the reading of data or the writing of a state "1" in the loop, while the other selection transistor controls the cancellation of the data and hence the writing of a state "0" by means of the grid arranged on the loop.

Abstract: A C-MOS semiconductor memory circuit includes a read amplifier and a tristate bus driver. The read amplifier is a two stage amplifier. The bit lines in the memory are connected via P-MOS pull-up transistors to the supply voltage. The logic low level is 1 Volt below the supply voltage. In order to bring the input signals for the difference amplifier at a most sensitive and fast level, a d.c.-shifting amplifier of the "emitter follower" type is connected between each input thereof and the associated bit line. The difference amplifier and the two follower amplifiers are activated only for a short period of time by means of a selection signal which gives a strong restriction in the power dissipation. The tristate driver comprises a push-pull output stage and an inverting AND gate which is controlled by the output of a difference amplifier and by an equalization signal which is also applied to the difference amplifier and therefore is of a simple design and gives only a low signal delay.

Abstract: A charge-coupled semiconductor device has a plurality of silicon electrodes for storing and transporting information-carrying charge, which electrodes are located on an insulating layer and are mutually separated by grooves having a width of at most 1 .mu.m. According to the invention, transfer electrodes are arranged in the grooves, these electrodes being coplanar with the remaining electrodes. The thickness of the insulating layer under the transfer electrodes is substantially equal to that under the storage electrodes. The invention also relates to a method of manufacturing a semiconductor device having such an electrode system.

Abstract: The operation of laser diodes requires a preset operating point. Owing to the spread in the characteristic curves of laser diodes, a costly adjustment is required for accurately determining this operating point, more specifically after each exchange of a laser diode. By using a control circuit, the operating point is positioned in the portion of the characteristic curve in which the ratio of the slope of the characteristic curve to the slope of the characteristic curve in the linear portion of the characteristic curve is equal to a predetermined value. This ratio is obtained by measuring the change in the bias current, which compensates for a power change caused by a change of the modulation current.

Abstract: In integrated semiconductor circuits having multilayer wiring, in which the circuit elements formed in the semiconductor body are interconnected by connection conductors which extend at at least two levels located one above the other and are mutually separated by insulating layers, undesired couplings may occur between the circuit elements and the conductor tracks extending above them. These disturbing couplings can be avoided by having at least one connection conductor of a lower wiring level so positioned and shaped and connected to such a potential that it constitutes a screening element between at least one underlying circuit element and at least one connection conductor at an upper wiring level.

Abstract: A semiconductor device for producing electro-magnetic radiation consisting of a radiation-emitting element (LED or laser) and an injection element, which can inject hot charge carriers into the active layer of the radiation-emitting element composed of layers of one conductivity type. With the use of active layers having a large band gap, for example GaN, short-wave light can be generated. According to the invention, the radiation-emitting element and the injection element constitute parts of the same epitaxial layer structure, the active layer being connected to the injection element by means of a semiconductor connection layer having a band gap larger than that of the active layer and that of the adjoining layer of the injection element.

Abstract: The invention relates to a charge-coupled device of the accordion type provided with a shift register for supplying accordion clock voltages on the one hand and with clock lines for supplying conventiional clock voltages on the other hand. The electrodes are alternatively coupled to the shift register and to the clock lines. The dissipation can be considerably reduced in this device. Moreover, the transport direction can be reversed in a simple manner, which is of importance, for example, in image sensors for smear suppression.

Abstract: The invention relates to a charge-coupled device with an adjustable charge transport route having at least two ccd segments, which can be connected in series with each other by means of a switchable connection. This connection includes an output diode for the first segment, an input diode for the first segment, an input diode for the second segment and a switch, for example a MOS transistor, which is connected to the output diode and/or the input diode. The input diode and the output diode may be in the form of individual zones or in the form of individual zones or in the form of a common zone. The invention, which offers the advantage that the transport time through the connection independent of the length of the form of the connection, can be used, for example, in programmable filters, (de)multiplexers, (de)scramblers and the like.

Abstract: A semiconductor monolithic integrated circuit comprising circuit elements built into isolated epitaxial layer islands is described. The isolation is accomplished by part by a p-n junction between the epitaxial layer and its substrate, in part by an insulated zone of converted epitaxial material sunken only part way through the layer, and in part by a depletion layer or buried zone of the substrate conductivity type.

Abstract: A flip-flop (40) for a divide-by-2 frequency divider having a first stage (50) formed by two master-slave-type memory elements (10a, 10b) each having a two-input NOR gate (20a, 20b), and by a second stage (60) with 2 NOR gates (61, 62) connected as an RS flip-flop. The memory elements (10a, 10b) also include an enhancement-type MESFET transistor (30a, 30b), the gates (Ga, Gb) and the drains (Da, Db) of said transistors (30a, 30b) being coupled to the respective inputs of the NOR-gates (20a, 20b).

Abstract: In conventional logic buffer circuits, internal signal overshoot during switching transitions causes power supply spikes or bounce, which may in turn degrade the operational reliability of other circuits in the same system. By using a pair of current amplifier circuits within the logic buffer circuit to shunt a portion of the signal overshoot, the output current of the logic buffer circuit is caused to change linearly with time, so that power supply bounce or spikes are substantially reduced.

Abstract: A semiconductor device comprising a first region, which is laterally bounded by a second region comprising a countersunk oxide layer and a highly doped polycrystalline silicon layer, which is disposed thereon and is covered by an oxide layer partly countersunk into it. The side edge of the polysilicon layer adjoins a contact zone, which is obtained by diffusion therefrom and is connected via a current path to a zone of a semiconductor circuit element. The upper side of the polysilicon layer is located at a higher level than that of the first region and the contact zone is connected to the said zone of the semiconductor circuit element via an intermediate region located in the first region below the second oxide layer and having a lower doping than the contact zone.

Abstract: A power integrated-circuit device is protected against load voltage surges. This is done by providing an alternate current-carrying path that is activated only in response to the occurrence of such surges. This alternate path is independent of and separate from the connection that extends between the device and its power supply source. In addition, circuitry is connected to the device to limit the portion of the surge voltage that can appear across critical elements of the device.

Abstract: A method of manufacturing a hetero-junction bipolar transistor, especially of gallium arsenide, comprising the step of forming superimposed epitaxial layers for forming a collector layer (1) of the n.sup.+ type, an emitter layer (3) of the n-type, the formation of localized implantations of the p.sup.+ type to obtain the base regions (31,30) or of the n.sup.+ type to obtain collector contact islands (20). This method also includes the formation by a controlled etching into a germanium layer (50) formed at the surface of these layers, of pads having a profile such that their tips define with a very high precision openings (E.sub.1), of which the distance (E.sub.0) between the edges defines the emitter contact region, while their edges have a concavity turned towards the exterior of the device.Application integrated circuits on gallium arsenide.

Abstract: A method of manufacturing a hetero-junction bipolar transistor especially of gallium arsenide comprising the formation of epitaxial layers superimposed to obtain a collector layer (1) of the n.sup.+ type, an emitter layer (3) of the n-type, the formation of localized implantations of the p.sup.+ type to obtain the base region (31, 30) or of the n.sup.+ type to form collector contact islands (20). This method also including the formation of base contacts B (70) having the dimensions B.sub.0 and located at a relative distance of E.sub.1, then covering the metallization (70) of pads (81) of silica (Si.sub.3 N.sub.4) having edges perpendicular to the plane of the layers on which bear spacers of silicon nitride (Si.sub.3 N.sub.4) (52) having dimensions h.sub.1 defining with a high precision the dimension E.sub.0 =B.sub.1 -2h of the emitter contact E and the distances between the different collector (90), base (70) and emitter (90) contacts C, B and E, respectively.

Abstract: The stability of semiconductor cathodes is improved by reducing the effective emitting surface area. This is effected by producing emission patterns by means of separate emission regions, whose overall surface area is much smaller than that of the actual emission patter. Due to the higher emission current and adjustment current, adsorbed particles, which adversely affect the stability of the emission, are rapidly drained.

Abstract: A charge-coupled device has a semiconductor body defining a charge transfer channel. Charge storage and charge transfer electrodes are provided for, respectively, defining charge wells within the charge transfer channel and transferring charge between charge wells. Two clock lines provide clock signals to the charge storage and transfer electrodes for controlling movement of charge between charge wells and to an output connection of the charge transfer channel. Signal processing means in the form of a sense amplifier are provided for processing an output from the charge transfer channel and a conductive path connects the output connection and the signal processing means. The conductive path crosses at least one of the clock lines and a conductive shielding layer extends between and is electrically isolated from the said at least one clock line and the conductive path.

Abstract: A semiconductor device includes a bipolar transistor having an emitter region of one conductivity type formed in a base region of the opposite conductivity type, the base region being provided in a collector region of the one conductivity type. A first insulated gate field effect transistor provides a gateable connection to the emitter region of the bipolar transistor while a second insulated gate field effect transistor provides a charge extraction path from the base region when the bipolar transistor is turned off. The first insulated gate field effect transistor includes a further region of the other conductivity type provided in the emitter region, and a source region of the one conductivity type formed in the further region and an insulated gate overlying a channel area comprising at least part of the further region to provide a gateable connection between the emitter region and the source region of the first insulated gate field effect transistor.