Abstract: The invention relates to a semiconductor device including a charge transfer device having an output stage (8). The output stage (8) has a read-out zone (9), a feedback capacitor (11) and an amplifier (10). An inverting input (15) of the amplifier (10) is connected to the read-out zone (9) and an output (16) of the amplifier (10) is fed back via the feedback capacitor (11) to the inverting input (15). According to the invention, the capacitor (11) is a capacitor of the MOS type and means are provided by which during operation of the charge transfer device the surface potential of a surface region (13) in the capacitor (11) is solely determined by the potential of the read-out zone (9). Consequently, the capacitance of the feedback capacitor (11) is dependent upon the potential across it, as a result of which there is a linear relation between the charge supplied to the read-out zone (9) and the voltage variation across the capacitor (11 ).

Abstract: In dynamic memories, generally a fluctuation of 10% of the nominal value of the supply voltage is allowed. Since, when reading, the input gate is applied to the supply, this fluctuation in the supply results in 20% of fluctuation in the charge packet formed below the input gate. In order to eliminate this fluctuation and hence to increase the permitted interference margin for other interference sources, a voltage stabilization circuit is arranged between the supply voltage and the input gate so that the fluctuation in the supply also occurs at the source zone, as a result of which the size of the charge packet becomes independent of the supply. For the voltage stabilization circuit, use may advantageously be made of a band gap reference.

Abstract: A semiconductor device includes a substrate of a first conductivity type, a semiconductor layer of the second opposite conductivity type disposed thereon and a lateral high-voltage transistor provided therein and located above a buried layer of the second conductivity type. Between the base zone and the surface-adjoining collector contact zone is situated a FET having an gate electrode separated from the semiconductor layer by a barrier layer. The gate electrode is electrically connected to the emitter. As a result, with the use of the transistor in emitter follower arrangement in the situation in which the emitter is substantially at collector potential, the emitter-collector current is not pinched off.

Abstract: A high-frequency circuit includes a field-effect transistor having a gate electrode for receiving a high-frequency input signal, a source electrode and a drain electrode. Substantial improvements in both maximum gain and high-frequency performance are achieved by providing an input or output terminal at one end of each electrode, and terminating at least one of the electrodes with an appropriate impedance at its second end.

Abstract: An integrated circuit has an on-chip supply voltage reducer, and includes a voltage converter for periodically charging the integrated circuit capacitance. The voltage converter may include a power switching transistor which is connected between an external supply terminal and an internal supply terminal and which is controled by a detector amplifier which senses the voltage across the integrated circuit capacitance connected to the internal supply terminal and which turns the switching transistor on and off depending on the value sensed, with a given hysteresis.

Abstract: An integrated variable resistor in MOS technology includes two parallel-connected transistors (T1, T2) whose electrodes are floating relative to the substrate (8). Its resistance is controlled by means of current sources (3, 4, 5, 6) whose current flows through the transistors (T3, T4) arranged as resistors. The body effect in the transistors (T1, T2) is compensated for by an equally large body effect in the transistors (T3, T4).

Abstract: The invention relates to an additional transistor which is connected in cascode with a sub-circuit of a logic circuit in order to protect further transistors of the sub-circuit against hot carrier stress and hot carrier degradation. In a logic circuit having transistors of a first conductivity type, an additional transistor of the second conductivity type is arranged in cascode. This additional transistor is connected as a diode or as a current source in dependence on an output voltage of the circuit. Further aspects of the invention concern the switching means for switching the additional transistor and the location where the additional transistor is to be inserted.

Abstract: A switched capacitor network includes an input terminal (2) an output terminal (2), a series arrangement of a first and a second switching transistor, each having a control electrode (S.sub.1) for receiving a first (S.sub.1 ) and a second switching signal, respectively, and a capacitance between the junction point of the two switching transistors and a point of constant potential. The two switching transistors have a zone in common and the capacitance (S.sub.s) is exclusively constituted by the parasitic capacitance of the zone (17). This structure results in a switched capacitor network with an increased time constant.

Abstract: A transistor output stage including an output transistor having its base coupled to the emitter of a driver transistor is driven into saturation by a current source which is connected to the base of the driver transistor. When a small output current is flowing through the load connected to the collector of the output transistor, the surplus of the current from the current source is drained from the base of the driver transistor to the collector of the output transistor via the collector-emitter path of a limiting transistor having its base connected to the base of the output transistor. This reduces the power dissipation in the driver transistor and improves the power efficiency of the transistor output stage.

Abstract: A semiconductor diode laser array, in which the active regions (3) are arranged in at least two groups, which are located in (two) substantially equidistant planes (V and W). At least one of the groups should comprise at least two active regions.According to the invention, the active regions (3) of one group located in the plane V are fully separated by at least one of the enclosure layers, for example the enclosure layers 2 and 4 (FIG. 1) or the enclosure layer 4 (FIG. 4) from the active regions 3 of the other group located in the plane W.

Abstract: In integrated logic circuits, at least one additional transistor may be provided in cascode connection with at least one other component in order to avoid detrimentally high electrical fields in components of such circuits. The control electrode is then connected to one of the power supply lines. When the state of the logic circuit changes, switching currents generate voltage peaks on the power supply lines due to the inductance of these lines. Via the chip capacitance these voltage peaks jump from one power supply line to the other. Thus, a positive feedback loop is formed which comprises one power supply line, the chip capacitance, the other power supply line and the additional transistor. Instabilities in such circuits are damped by inserting a resistance element between the control electrode of the additional transistor and the power supply line coupled thereto.

Abstract: An integrated CMOS circuit having a transistor located in a p (or an n) well and a adjacent complementary transistor. The transistors are located in an epitaxial layer on a highly doped substrate. With use, for example, in bridge circuits having an inductive load, parasitic currents can occur, which give rise to "latch-up" and/or dissipation. This can be avoided by providing under the source zone of the transistor located beside the wells a second region having substantially the same doping and depth as the well, which is connected to the source zone.

Abstract: The invention relates to an integrated circuit having a lateral transistor, whose emitter region has a depth and a doping level such that the diffusion length of the minority charge carriers vertically injected into this region is greater than or equal to the thickness of the said region, the ratio between the surface of the emitter region and that of the electrical connection emitter zone being at least equal to 20. The current amplification .beta. of such a transistor is considerably increased by giving the emitter region an elongate shape in a longitudinal direction, the ratio between the largest longitudinal dimension and the largest transversal dimension being at least equal to 5.

Abstract: The invention relates to a charge transfer device (CTD) having two or four phases, for which the speed of transferring the stored charges is increased by means of self-induction members connected to each of the clock areas of each memory element so that the capacitive impedance presented initially to the clock signal generator by the CTD becomes a substantially resistive impedance. Such a charge transfer device having an increased transfer speed is used in digital oscilloscopy or in systems for handling pictures.

Abstract: A push-pull output circuit which is powered by a 5-V supply voltage and in which the "push" part comprises a PMOS transistor and the "pull" comprises a PMOS transistor and an NMOS transistor. The NMOS transistor is driven via a detection circuit so that no hot carrier stress occurs in the NMOS transistor.

Abstract: An integrated circuit includes capacitances of different capacitance values, this circuit having rows of basic capacitances, while the capacitances have different numbers of basic capacitances connected in parallel between a first connection electrode and an associated second connection electrode. Plural rows have the same number of n basic capacitances and in different ones of these rows different numbers of basic capacitances form part of the capacitances, all the remaining basic capacitances of the relevant rows being dummy capacitances. The second capacitance electrodes are connected to one or more further connection electrodes.

Abstract: Low voltage semiconductor devices are integrated monolithically with a high voltage semiconductor device on an electrically conductive substrate. The substrate forms an electrode of the high voltage device and is connected in use to the high voltage terminal of a power supply. The low voltage devices operate from a regulated low voltage supply, which is regulated with reference to the high voltage supply voltage, and not with reference to ground. This reduces the need to isolate the low voltage devices from the conductive substrate. An intelligent power switch circuit constructed in accordance with the invention is suitable for use in automotive and lighting applications.

Abstract: Current flow through the base region of a hot charge-carrier transistor is by hot majority charge-carriers (i.e. hot electrons for a hot electron transistor) which are collected at a base-collector barrier. This barrier may be formed by a semiconductor region which is doped with an impurity of the opposite conductivity type (p type for a hot electron transistor) and which is sufficiently thin as to form a bulk unipolar diode with an adjacent part of the base region. In accordance with the invention, one or more layers of wider-bandgap semiconductor material (for example, gallium aluminum arsenide) are present within the collector region (for example, of gallium arsenide) to form one or possibly even a series of heterojunctions each providing an electric field which retards the hot charge-carriers in the collector region. The retarding field cools the hot charge-carriers after collection so reducing a tendency to create electron-hole pairs by ionization.

Abstract: A digital circuit with a 5 V power supply voltage in which NMOS transistors constructed in sub-micron technology are protected against excessive field strengths by means of additional transistors in order to prevent so-called "hot carrier stress" for this purpose the additional transistors have a greater channel length and/or a higher threshold voltage.

Abstract: A third-order all-pass network for a delay circuit is formed by four coupled transconductors (G.sub.10 to G.sub.13) which are each represented by two transistors whose bases constitute the inputs and whose collectors constitute the outputs of the transconductor. A first input of these transconductors (G.sub.10 to G.sub.13) is connected to ground (3). Between the second inputs (25,26) of the first transconductor (G.sub.10) and the second transconductor (G.sub.11) a first capacitor (C.sub.1) is arranged, between the second inputs (26,27) of the second transconductor (G.sub.11) and the third transconductor (G.sub.12) a second capacitor (C2) is arranged, and between the second inputs (27,28) of the third transconductor (G.sub.12) and the fourth transconductor (G.sub.13) and a third capacitor (C3) is arranged. Further, a fourth capacitor (C4) is arranged between the second inputs (25,27) of the first transconductor (G.sub.10) and the third transconductor (G.sub.