Abstract: A memory cell is read by first charging a pair of bit lines to given positive potentials and then raising the potential of a cell access line to render access transistors conductive. The cell supply voltage is sufficient to cause substantial hot-electron stress in the n-channel transistors of the cell if it were applied directly across their source-drain paths while they were conductive. However, a limit is imposed on the maximum positive potentials which are applied to the bit lines from the exterior, and on the minimum ratio of the sizes of the cell n-channel amplifier transistors to the sizes of the access transistors, taking into account the threshold voltages of the amplifier transistors, and as a result substantial hot-electron stress does not occur. Substantial hot-electron stress is also prevented during a write operation by arranging that this is effectively preceded by a read operation.

Abstract: A semiconductor device includes a silicon layer of a first conductivity type, which is disposed on a dielectric substrate and in which at least two zones of a semiconductor circuit element of a second opposite conductivity type and a contact zone having the same conductivity type as, but a higher doping concentration than the silicon layer are provided, which zones adjoin a surface of the silicon layer. According to the invention, the contact zone extends below the zones of the field effect transistor. This semiconductor device has the advantage that it can be manufactured in a very simple manner. In a method of manufacturing this device, in a silicon layer of a first conductivity type disposed on a dielectric substrate are formed a contact zone having the same conductivity type as, but a higher doping concentration than the silicon layer and at least two zones of a semiconductor circuit element of a second opposite conductivity type.

Abstract: A lateral MOS transistor includes a semi-insulating field plate adjacent the surface of the device, over the drift region and extending laterally from the drain electrode toward the gate and source electrodes of the transistor. The field plate is connected at one end to the drain electrode, and at the other end to either the gate electrode of the source electrode. In order to improve the turn-on characteristics of the transistor, a surface-adjoining semiconductor top layer is provided in the drift region of the device, between the channel region and the drain region. This top layer is connected to the channel region at selected locations, and serves to improve device turn-on performance by causing a more rapid decrease in ON resistance at turn-on.

Abstract: An integrated matrix memory includes standard sub-blocks and a redundant block. Each of the standard sub-blocks has a fixed number of standard sub-blocks, and the redundant block has one or more redundant sub-blocks. For addressing there is provided a detector for the address of a faulty standard sub-block. In that case a redundant sub-block is selected. Selection is realized by way of a sub-bus which forms part of the data path. Thus, a redundant system is achieved in which delay is minimized.

Abstract: A semiconductor device includes at least one field effect transistor integrated monolithically on a substrate with a decoupling diode between a d.c. supply conductor and a ground conductor. The transistor is preferably a MESFET formed in a first semiconductor layer of the n-type preferably made of a III-V material. According to the invention, the decoupling diode is constituted by the ground conductor forming a Schottky junction of large surface area polarized in the opposite sense with a second semiconductor layer of the n-type, the supply conductor being resistively connected to the second semiconductor layer. According to a preferred embodiment, the second layer also comprises the resistive load of the transistor.

Abstract: A method of manufacturing a semiconductor device of the "planar" type comprising a highly doped substrate having a doping concentration c.sub.o and an epitaxial surface layer having a carrier concentration c<c.sub.o, in which are formed a main pn junction having a depth x.sub.j and a structure of floating guard rings. According to the invention, this device also includes between the substrate and the epitaxial surface layer, a second epitaxial layer having a carrier concentration c' such that c.sub.o >c'>c. This permits the production of devices with different maximum operating voltages using the same configuration of guard rings.

Abstract: A temperature controlled crystal oscillator circuit comprising an amplifier (12) having a feedback path including a crystal (26) and a frequency pulling element (28), and a temperature compensating voltage generating circuit (30) coupled to the frequency pulling element (28). The voltage generating circuit (30) produces a voltage, V.sub.comp, generated in accordance with the following function:V.sub.comp =b*exp[a1(T-T.sub.R)]+b*exp[-a2*(T-T.sub.R)]+c*(T-T.sub.R)whereT.sub.R is a reference temperature in degrees KelvinT is the working temperature in degrees Kelvina1, a2, b and c are constants.

Abstract: Package for a very high frequency integrated circuit comprising a housing provided with a recess whose bottom is metallized and provided with peripheral connectors, and including a connection device inserted in the recess between the integrated circuit and the connectors, this connection device including a substrate that presents an upper surface comprising microstrip lines to connect contact studs of the integrated circuit to the connectors of the housing and a metallized lower surface to form a ground plane.

Abstract: The invention relates to an integrated circuit having a transistor suitable for integrated injection logic (I.sup.2 L) with a single collector output region and having at least one base contact disposed between the collector output region (C.sub.60, C'.sub.60) and the injector (IN.sub.6), the surface of the collector output region being several times larger than that of a logic gate of the I.sup.2 L multi-collector type. The base (B.sub.60) has at least two rows of interconnected contacts: a first row (CB.sub.60, CB.sub.61, CB.sub.62) constituting the base contact disposed between the collector and the injector, and at least a second row (CB.sub.63, CB.sub.64, CB.sub.65) situated at the perimeter of the collector (C.sub.60,C'.sub.60), which can consist of one or several parts. The injector (IN.sub.6) may also have a row of interconnected contacts (CIN.sub.1, CIN.sub.2, CIN.sub.3).

Abstract: An integrated circuit includes a memory having cells arranged in rows and columns, each cell having transistor being connected between two bit lines and having a current channel, a control gate and a charge-storage region therebetween, neighboring cells in a same row having a bit line contact in common, and control gates of transistors in a row being connected to a same word line, wherein each transistor has in a substrate of a first conductivity type a source region, a drain region and an injector region of a second conductivity type and mutually separated from each other, the injector regions of the transistors in a first row being controllable via the bit line contacts of the transistors in a second row adjacent to said first row. Preferably, at least one source region, at least one drain region and at least one injector region that are connected to a same bit line contact form a coherent region, e.g. a well, in the substrate. Preferably, the first and second row have the word line in common.

Abstract: In a charge-coupled SPS memory device, in which the transport takes place according to the "pushing" principle, it may occur that during the SP transport charge is injected into the substrate and diffuses via the substrate into the memory mat. In order to avoid this undesired injection of charge, the input is provided with means by which it is ensured that the storage site under the input gate is entirely empty during the SP transport.

Abstract: An integrated memory circuit in which memory cells are arranged in rows and columns, each column having a separate sense amplifier. The memory columns can be coupled to neighboring memory columns by additional transistors and the gain of the sense amplifiers in the even and the odd columns is adjustable. Consequently, information can also be serially shifted from one column to another, so that the information can be written and read not only in parallel but also serially.

Abstract: A delay line, especially for delaying t.v. signals, includes a series of signal storage capacitances, an input line, an output line, selection transistors between the storage capacitances and the input and output lines and a digital shift register for activating the selection transistors. According to the invention, the output line comprises a central part, on either side of which signal storage capacitances with associated selection transistors are located, which in turn are located between the central part of the output line and the associated parts of the shift register. The design according to the invention results in a compact configuration, which has the advantage that the parasitic capacitance of the output line is comparatively low. The configuration can be readily extended to two interlaced delay lines having a single common shift register.

Abstract: For satisfactory operation of a display arrangement having an electro-optical display medium and picture elements arranged between row and column electrodes and connected in series with an anti-parallel arrangement of PIN diodes, the diodes should have a small reverse current notwithstanding any ambient radiation present. In a display arrangement according to the invention, a small photo-current in the reverse direction is obtained due to the fact that the i-region and the p- or n-type region do not adjoin each other directly in the proximity of the edge of the mesa-shaped PIN diode. The region within which the aforementionhed regions adjoin each other is preferably located at a distance from the edge of the mesa-shaped PIN diode amounting to at least once the penetration depth of the ambient radiation plus the diffusion length of charge carriers in the i-region.

Abstract: An integrated semiconductor circuit, in which the D.C. part of the wiring containing only D.C. information lies on a part of the insulating layer located on the surface which is considerably thinner than the parts of the insulating layer under wiring parts not forming part of the D.C. wiring. Preferably, for this purpose a substrate contact diffusion connected to a reference potential is provided under the D.C. wiring parts. As a result, H.F. interference signals on the D.C. wiring are reduced so that noise and distortion are considerably reduced.

Abstract: An integrated memory circuit includes a high-voltage switch which is connected between a programming voltage generator and an erasable programmable memory. In the preferred embodiment of the memory circuit, the switch includes a first transistor of the field-effect enhancement type which is connected between a high-voltage point and a control electrode of a second transistor, also being of the field-efffect enhancement type, which is connected between the high-voltage point and the control electrode of the first transistor. By driving the two control electrodes by means of mutually complementary clock signals, via a capacitance, the programming voltage is step-wise built up on the control electrodes of the cross-wise coupled transistors. The switch is less susceptible to crosstalk on the clock lines and is realized using fewer masking steps than the prior art switch.

Abstract: A first charge storage electrode (21) has a first row (21b) of teeth interdigitated with a second row (22b) of teeth of a second charge storage electrode (22). The second storage electrode (22) has a third row (22c) of teeth interdigitated with a fourth row (23b) of teeth of a third charge storage electrode (23). The first and third rows (21b and 22c) overlie one group (11b) of a series of parallel conduction channels while the second and fourth rows (22b and 23b) overlie another group (11a) of the parallel channels. A first charge transfer electrode (24) is provided to transfer charge packets into sites beneath the first storage electrode.

Abstract: The invention relates to an electric element, whose conductance is quantized in units 2e.sup.2 /h realized in a multi-dimensional charge carrier gas, which is provided with a part of reduced width having a width of the order of the Fermi wavelength and a length smaller than the average free path length. Due to the small width of the part of reduced width, the energy levels are subdivided, as a result of which, at a temperature at which the distance between the levels is comparable with kT, the charge transport through the constriction is determined by quantum-mechanical effects. For the charge carrier gas, for example, a two-dimensional electron gas near a GaAs-AlGaAs hetero-junction may be used, for example, in a voltage divider.

Abstract: A tunable semiconductor diode laser with distributed reflection (DBR semiconductor laser) having a wide wavelength range is a suitable transmitter or local oscillator in a receiver in heterodyne and coherent optical glass fiber communication systems. Such a diode includes, in addition to the Bragg section in which the Bragg reflection takes place, an active section in which the radiation-emitting active region is present. When such a semiconductor diode laser is further provided with a so-called phase section, tuning is possible over a large wavelength range within one oscillation mode. A laser which is continuously tunable over the whole wavelength range is obtained by provided a mechanism by which the intensity of radiation which is reflected at the junction between the active section and the phase section is made low with respect to the intensity of the radiation which returns from the phase section to the active section.

Abstract: A lateral insulated gate transistor includes both a surface-adjoining drain region and a surface-adjoining anode region in an epitaxial surface layer. An anode-drain electrode is connected to the anode region and coupled to the drain region. In one embodiment of the device, the drain and anode regions are in direct contact, and the anode-drain electrode directly contacts both regions. In a second embodiment, the anode region is provided in a high-doped surface-adjoining region rather than in direct contact with the drain region, and the anode-drain electrode is coupled to the drain region through a resistive element. A third embodiment employs a Schottky contact connected to the anode-drain electrode. Lateral isolated gate rectifiers in accordance with the invention offer the advantages of low "on" resistance, high breakdown voltage and fast switching characteristics.