Abstract: A method of testing an interconnection function between two integrated circuits which are mounted on a carrier and which are interconnected by data connections, for example a printed wiring board, is disclosed. The integrated circuits are also connected to a serial bus via which test patterns and result patterns can be communicated between a test device which can be connected thereto and the respective integrated circuits. The bus of a preferred embodiment is formed by a so-called I.sup.2 C bus. In a further elaboration, this set-up can also be used for testing the internal logic circuitry of the integrated circuits. For the testing of the interconnection function, input/output cells with a parallel connection for performing the normal execution function in a transparent mode are provided. They also include series connections for communication test/result patterns by way of a shift register.

Abstract: A two-lead starter circuit for a gaseous discharge lamp is composed of only four components, namely a capacitor, a bilateral voltage-sensitive switch, a pulse transformer and a resistor. These components are connected in a series-parallel circuit arrangement which is both more economical and more reliable than prior-art two-lead starter circuits.

Abstract: A semiconductor laser having a buried hetero junction, more particularly a DCPBH laser, in which the active layer (3) is located in a "mesa", which is laterally bounded by a boundary region comprising at least one blocking layer (6) having a larger band gap than the active layer. The boundary region includes an absorption layer (13) having a smaller band gap than the active layer, this absorption layer being located at such a small lateral distance from the active layer that it lies within the amplification profile of the first-order lateral oscillation mode. As a result, the first and higher oscillation modes as well as the thyristor effect are suppressed.

Abstract: In a one-electrode/bit SPS CCD memory, a capacity reduction can be obtained by phase shift of one or more clock voltages. For an n-phase system with N groups of n electrodes, the storage capacity can thus be reduced stepwise from at most N(n-1) bits to N(n-2) bits, etc. The stay time of the bits stored is reduced by a corresponding factor, as a result of which the clock frequency in the series registers need not be changed. By this reduction, the memory is more particularly suitable for storing television pictures both in the 625 lines system and in the 525 lines system.

Abstract: A semiconductor laser of the double hetero-junction type has a current-limiting buried blocking layer with a second active layer and an additional passive layer provided above the first layer. As a result, the threshold current required for laser operation is less strongly dependent upon temperature. At the same time, the radiation intensity versus current strength characteristic of the laser above the threshold current is substantially straight, without the presence of "kinks".

Abstract: A semiconductor device includes a silicon layer of a first conductivity type, which is disposed on a dielectric substrate and in which at least two zones of a semiconductor circuit element of a second opposite conductivity type and a contact zone having the same conductivity type as, but a higher doping concentration than the silicon layer are provided, which zones adjoin a surface of the silicon layer. According to the invention, the contact zone extends below the zones of the field effect transistor. Thus, it is counteracted that at an interface of the silicon layer and the substrate a channel is formed which shortcircuits the zones. Moreover, the semiconductor device has a constant threshold voltage. This semiconductor device has the additional advantage that it can be manufactured in a very simple manner.

Abstract: A logic level converter circuit has a first state (E.sub.1 low, E.sub.2 low) which produces a high level on the output TTL S, a second state (E.sub.1 high, E.sub.2 low) which produces a low level on the output S, and a third state (E.sub.2 high) which a very high impedance in which the two output transistors T.sub.5 and T.sub.6 are turned off. The current of a current source I.sub.1 is directed by the transistors T.sub.1, T.sub.2, T.sub.7, T.sub.8 and T.sub.9. In the second state and the third state, a diode D.sub.3 which bridges the bases of the transistors T.sub.5 and T.sub.6 (points A and B) is conductive, while a diode D.sub.2, connected between ground and the point A, is conductive in the third state.

Abstract: A memory incorporates redundancy in the form of one or more redundant columns. An applied binary address is first distributed between predecoders which form a 1-out-of-2.sup.n code from n bits received. For each non-redundant column there is available a part of a main decoder, each part receiving a different combination of the bits supplied by the predecoders, thus selecting the column. For each redundant column there is provided a redundancy decoder. The latter decoder receives all bits supplied by the predecoders, each time via a series connection of a activatable gating element and a fuse element. Per predecoder the outputs of the series connections are combined in a wired logic function. Each wired logic function forms an input signal of the actual redundancy decoder. When a redundant column is to be addressed, all fuse elements but one of a group are opened and the gating elements are activated. A memory column to be replaced is then uncoupled by way of another fuse element.

Abstract: A high mobility p channel semiconductor device (such as a field-effect transistor) is suitable for operation at room temperature, for example in a circuit with an n channel device. Whereas hole modulation doping both in single heterojunction and in heterostructure quantum well devices provides a significant increase in hole mobility only at cryogenic temperatures, the present invention employs less than 5 nm wide and very deep quantum wells (about 0.4 eV and deeper) to reduce the effective mass of "heavy" conduction holes for motion in the plane of the quantum well. Hole mobilities at 300 degrees K. are obtained in excess of 2.5 times those in bulk material of the same narrow bandgap semiconductor as used for the quantum well. In a particular example such a quantum well is formed of GaAs (or GaInAs) between AlAs barrier layers.

Abstract: In a semiconductor device (e.g. a fast switching Schottky diode) a metal-based layer forms separate areas of an active Schottky barrier between closely-spaced field-relief regions which provide the device with an improved voltage blocking characteristic. In order to restrict the flow of minority carriers into the adjacent body portion under forward bias, the dopant concentration of the field-relief regions at the surface where contacted by the metal-based layer is sufficiently low as to form a further Schottky barrier with the metal-based layer. This further barrier which is in series with the minority-carrier injecting p-n junctions of the field-relief regions is reverse-biased when the active barrier and p-n junction are forward biased so that the minority carrier injection is restricted by the leakage current across the further barrier.

Abstract: In programmable memories of the EPROM or EEPROM type, a row and/or column of test memory cells are added to the matrix of rows and columns of non-volatile memory cells for the testing of the peripheral circuits which select and read the memory cells. The test memory cells have a very short write time as compared with the non-volatile memory cells and may be of the dynamic (or volatile) type. The write time for a memory cell of the EPROM or EEPROM may be, for example, 10 msec. The write time for a dynamic memory cell, however, is 100 nsec. The time required for testing the peripheral circuits can therefore be reduced by a factor of 80 (for a 16 Kbit memory) or higher (for memories larger than 16 Kbits).

Abstract: A high-frequency transistor having a substrate of a first conductivity type, an epitaxial collector layer of the first conductivity type, a layer-shaped base region of the second opposite conductivity type, which is provided in the collector layer and is subdivided by a sunken oxide pattern into a number of base zones which are interconnected by conducting layers located on the oxide pattern, and at least one emitter zone of the first conductivity type in each base zone. According to the invention, the conducting layers consist of poly-crystalline silicon of which an edge is covered with a thin oxide layer which extends into the base zone and laterally bounds the emitter zones.

Abstract: A radiation-sensitive semiconductor device has a high-ohmic semiconductor wafer with a thicker edge portion and a thinner central portion, in which a photodiode is located. The surface opposite to the photodiode is provided with a highly-doped contact layer, on which a metal layer is provided. The central portion is so thin that at a low photodiode voltage the depletion zone of the photodiode extends as far as the contact layer. According to the invention, the device includes an active screening diode, which extends both in the edge portion and in the central portion and whose depletion zone extends in the operating condition in the central portion as far as the contact layer. As a result, diffusion of charge carriers from the edge portion to the photodiode is avoided.

Abstract: A third-order all-pass network for a delay circuit is formed by four coupled transconductors (G.sub.10 to G.sub.13) which are each represented by two transistors whose bases constitute the inputs and whose collectors constitute the outputs of the transconductor. A first input of these transconductors (G.sub.10 to G.sub.13) is connected to ground (3). Between the second inputs (25,26) of the first transconductor (G.sub.10) and the second transconductor (G.sub.11) a first capacitor (C.sub.1) is arranged, while between the second imputs (26,27) of the second transconductor (G.sub.11) and the third transconductor (G.sub.12) a second capacitor (C2) is arranged, and between the second inputs (27,28) of the third transconductor (G.sub.12) and the fourth transconductor (G.sub.13) a third capacitor (C3) is arranged. Further, a fourth capacitor (C4) is arranged between the second inputs (25,27) of the first transconductor (G.sub.10) and the third transconductor (G.sub.

Abstract: A semiconductor cathode is realized with the aid of a pin structure in which the intrinsic semiconductor region includes a first region with a small band distance and a second region with a large band distance. Consequently, at a sufficient reverse voltage, electrons (6) are generated in the first region (6) which electrons tunnel from the valence band to the conduction band and have a sufficient potential energy to be emitted from the semiconductor body.

Abstract: Memory cells in an integrated memory circuit are arranged in blocks and selected by block selection gates. This method of activation offers the advantage that the memory cells are accessed faster and that the power consumption is lower than in a memory which is not subdivided into blocks, because only a small group of memory cells is activated per selection operation. A block selection circuit is provided in which selection gates of two neighboring rows of memory cells have one common transistor. As a result of the multiple use of contact areas and the use of a mirror-symmetrical architecture, the lay-out can make optimum use of the available substrate surface area.

Abstract: A charge-coupled image sensor arrangement has an overexposure adjustment feature whereby the excess of generated electrons is drained in vertical direction to the substrate. In order to adjust the maximum acceptable extent of overexposure, an additional low voltage can be applied to the blocking gates. As a result, it is possible to adjust the maximum overexposure without the maximum white level being variable. Due to the fact that the blocking voltage is a d.c. voltage, the dissipation substantially does not increase.

Abstract: Current flow through the base region of a hot charge-carrier transistor is by hot majority charge-carriers (i.e. hot electrons for a hot electron transistor) which are injected into the base region at an emitter-base barrier region. This barrier region is doped with an impurity of the opposite conductivity type (p type for a hot electron transistor) and is sufficiently thin as to form a bulk unipolar diode with an adjacent part of the base region. In accordance with the invention, the emitter-base barrier region is of different bandgap semiconductor material (for example, gallium aluminum arsenide) compared with that (for example, gallium arsenide) of the base region so as to form a heterojunction. The barrier height of this barrier region is determined in part by the opposite-type doping and in part by the heterojunction and can be made large so as to increase the energy of the injected charge-carriers and hence the collector efficiency of the transistor.

Abstract: A semiconductor laser of the distributed feedback (DFB or DBR) type is bounded in the longitudinal direction by end surfaces at right angles to the active region and at least one of these end faces is provided with an anti-reflection layer in order to suppress Fabry-Perot modes. In order to obtain an optimum effect, an anti-reflection layer of hafnium oxide is used. The invention is used with great advantage in lasers of the DCPBH (Double Channel Planar Buried Hetero-structure) type.

Abstract: A monolithic integrated memory includes a differential read amplifier circuit which is associated with a column of the memory and which has two source-coupled field effect transistors, the coupling point of which is controlled by a current source which itself is controlled by the output signal of a decoder stage which enables the selection of the memory column. The gate of each coupled transistor receives the signal of a bit line of the memory column, while the drains of the coupled transistors apply a signal to the read bus of the memory. A translator circuit is provided for translating the levels of the signals transported by the bit lines in order to ensure that these levels are at most equal to the levels of the signals transported by the read bus, so that the gate-drain capacitances of the coupled transistors of the differential amplifier are negligibly small.