Abstract: One aspect of the present invention relates to a system and method for monitoring in-situ a chemical composition at or near a surface of a wafer during plasma etch to detect defects The method involves the steps of providing a semiconductor substrate comprising at least one top layer, wherein the semiconductor substrate comprises at least one chemical-containing contaminant; subjecting the semiconductor substrate to a plasma etch process, whereby at least a portion of the top layer is removed; during the plasma etch process, detecting for a presence of the chemical-containing contaminant using one of an Auger Electron Spectroscopy system or Energy Dispersive X-ray Analysis system; and if present, determining whether the presence of the chemical-containing contaminant exceeds a threshold limit.

Abstract: An exemplary method of fabricating an integrated circuit can include depositing a reflective metal material layer over a layer of polysilicon, depositing an anti-reflective coating over the reflective metal material layer, trim etching the anti-reflective coating to form a pattern, etching the reflective metal material layer according to the pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating.

Abstract: Test wafer consumption is a significant contributor to overall cost of manufacturing in semiconductor industry due to scrapping the test wafers after one monitoring of implantation parameters. This invention provides a method to reuse the same test wafer for monitoring the implantation parameters more than once. This method comprises the possibility of implanting the same implant species together with identical implanting and annealing conditions as well as of implanting a broad variety of implant species together with varying implanting and annealing conditions. Therefore, this invention helps to significantly reduce the number of test wafers consumed in the implant-area.

Abstract: A memory device that includes a charge trapping region disposed laterally adjacent a first end of a channel such that energetic electrons traversing the channel can be ballistically injected into the charge trapping region.

Abstract: The invention provides a system and process for depositing films, wherein an acoustic microbalance is used for process monitoring and/or control. The acoustic microbalance is placed in a deposition chamber and may optionally be mounted on a semiconductor substrate, such as a silicon wafer, on which a film is being deposited. Data from the acoustic microbalance is employed to detect a process endpoint, determine an adjustment to process conditions for a subsequent batch, and/or provide feedback control over current process conditions. One aspect of the invention involves the application of a model or database to correct for differences between the extent of deposition on an acoustic microbalance cantilever and the extent of deposition on a substrate being processed. Another aspect of the invention takes a probabilistic approach to employing acoustic microbalance data.

Abstract: The present invention is directed to a method and apparatus for performing polishing operations on substrates in an integrated circuit manufacturing environment. In one embodiment, the apparatus is comprised of a movable polishing platen, a polishing pad positioned on the platen, and a polishing arm that is adapted to receive and move the substrate relative to the polishing pad. The apparatus further comprises a first pad conditioner with a first conditioning surface that is positionable to allow contact between the first conditioning surface and the polishing pad, and a second pad conditioner with a second conditioning surface that is positionable to allow contact between the second conditioning surface and the polishing pad. In one embodiment, the method of the present invention comprises positioning a substrate to be polished in a polishing tool, supplying a polishing slurry to the tool, and providing relative movement between the substrate and a polishing pad.

Abstract: An integrated circuit provides for changes to its core clock frequency and its core voltage using software programmable registers on the processor to store voltage ID (VID) values to specify core voltage, which are supplied to a voltage regulator and clock frequency control values, which are supplied to clock generation logic on the integrated circuit to specify core clocks. The integrated circuit generates an internal state in which its core clocks are stopped or slowed and during which core voltage and core frequency are adjusted. The processor also includes a timing mechanism that allows the new voltage and clock frequency to stabilize before resuming core operations. The timing mechanism may include a programmable count to specify the time to allow the new voltage and clock frequency to stabilize.

Abstract: A method of fabricating nitride read-only memory (NROM) cells and arrays. The memory device is formed on a substrate. Each memory cell comprises a pair of bit lines extending in a first direction across the substrate, a pair of bit line dielectrics overlaying and covering the pair of bit lines, a charge-trapping layer formed over the channel region between the pair of bit lines, and a conductive connecting block formed on the charge-trapping layer. The charge-trapping layer comprising two oxide-nitride-oxide (ONO) structures separated by a gate oxide layer, where each ONO structures comprises a layer of nitride sandwiched between a bottom oxide layer and a top oxide layer. A plurality of straight, parallel-edged word lines extend across the substrate in a second direction and cross over the bit lines and channel regions. Each word line comprises a conductive material and is separated from the substrate by the conductive connecting blocks and bit lines dielectrics.

Abstract: An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.

Abstract: A technique in which a first boundary region is added to the ends of phase zero (0) pattern defining polygons and a second boundary region is added to the ends of phase 180 pattern. This technique can improve line end pattern definition and improve the manufacturability and patterning process window. The added boundary region balances the light on both sides of the line ends, resulting in a more predictable final resist pattern.

Abstract: A semiconductor device which includes a precision high-K dielectric and formed on a semiconductor substrate and a method of forming the same. The semiconductor device includes at least one dielectric layer having a dielectric constant greater than SiO2. The at least one dielectric layer is deposited by atomic layer deposition (ALD). The ALD deposited layer has precise uniformity, thickness and abrupt atomic interfaces.

Abstract: A method and an apparatus for reducing process non-uniformity across a processed semiconductor wafers. A first semiconductor wafer is processed. A process non-uniformity associated with the first processed semiconductor wafer is identified. A feedback correction in response to the process non-uniformity during processing of a second semiconductor wafer is performed and/or a feed-forward compensation is performed in response to the process non-uniformity during a subsequent process performed across the first semiconductor wafer is performed.

Abstract: One aspect of the present invention relates to a system and method for improving memory retention in flash memory devices. Retention characteristics may be enhanced by nitridating the bottom silicon dioxide layer of the ONO dielectric. To further mitigate charge leakage within the memory cell, the charge retention layer, or silicon nitride layer of the ONO dielectric, may be passivated via a hydrogen anneal process in order to reduce the number of charge traps, and thus, the amount of charge loss. The present invention also provides a monitoring and feedback-relay system to automatically control ONO formation such that a desired ONO dielectric stack is obtained. The present invention may be accomplished in part by employing a measurement system to measure properties and characteristics of the ONO stack during the critical formation steps of the bottom silicon dioxide layer and a silicon nitride layer.

Abstract: A mask generation method can enhance clear field phase shift masks using a chrome border around phase 180 regions. An exemplary method involves identifying edges of a 180 degree phase pattern, expanding these edges, and merging the expansions with chrome. An alternative method involves oversizing and undersizing phase 180 data, taking the difference, and merging the difference with chrome. The chrome region on the phase mask can improve mask generation by allowing the chrome on the mask to fully define the quartz etch.

Abstract: An apparatus for x-raying a semiconductor device which includes semiconductor material and conductive material, the apparatus including a source of x-rays, a filter for receiving x-rays from the source of x-rays and allowing transmission of x-rays to the device, the filter having an atomic number greater than the atomic number of the conductive material of the device, and an x-ray imager for receiving x-rays from the device.

Abstract: A non-volatile memory device comprising logic for charge restoration. The restore logic controls a read circuit for determining a value associated with the threshold voltage of a memory cell selected from a memory cell array, and compares the value to one or more boundary values to determine whether or not the memory cell value is out of bounds. In the event that the memory cell value is out of bounds, a target value for the memory cell is established. The restore logic controls a write circuit that applies a write pulse to the memory cell. The read and write process is repeated as necessary until the target value for the memory cell is achieved. The restore logic may include a processor for performing a statistical analysis on the memory cell array in order to determine target restoration values. Memory cells within the array may be reserved for use by the restore logic.

Abstract: A method for computer MSE to PE tables for rate negotiation has been disclosed. The method obtains probabilistic values for packet sizes in a network and obtains BER values for each FER based on these probabilistic values. An MSE for each PE is then calculated based on the BER values to obtain the upper limit tables. The MSE values in the upper limit tables is then decreased by 2 dB to obtain the lower limit tables. The MSE to PE tables may then be used for rate negotiation as set forth in the HPNA 2.0 specification.

Abstract: A method is provided for forming polysilicon line structures, such as gate electrodes of field effect transistors, according to which oxide spacers are removed from the sidewalls of the poly gate lines before depositing the liner oxide. Accordingly, after formation of the final spacers, the polysilicon line sidewalls are no longer covered with spacer oxide but all silicide pre-cleans can clear the poly sidewalls completely which thus leads to improved silicidation conditions, resulting in gate lines exhibiting very low sheet resistivity.

Abstract: The present invention is directed to a method of controlling chemical mechanical polishing operations to control the duration of an endpoint polishing process. The method comprises providing a wafer having a layer of copper formed thereabove, performing a first timed polishing operation for a duration (t1) on the layer of copper at a first platen to remove a majority of the layer of copper, performing an endpoint polishing operation on the layer of copper at a second platen to remove substantially all of the layer of copper, determining a duration (t2ept) of the endpoint polishing operation performed on the layer of copper at the second platen, and determining, based upon a comparison between the determined duration (t2ept) of the endpoint polishing operation and a target value for the duration of the endpoint polishing operations, a duration (t1) of the timed polishing operation to be performed on a subsequently processed layer of copper at the first platen.

Abstract: A silicon-on-insulator semiconductor device, including a silicon-on-insulator wafer having a silicon active layer, a dielectric isolation layer a silicon substrate, and at least one isolation trench defining an active island in the silicon active layer, in which the silicon active layer is formed on the dielectric insulation layer and the dielectric insulation layer is formed on the silicon substrate, in which the at least one isolation trench includes a layer of a passivating insulator in a lower portion of the isolation trench and in contact with the dielectric insulation layer. The passivating insulator prevents formation of a bird's beak between the silicon active layer and the dielectric insulation layer during subsequent fabrication of the isolation trench.