Abstract: Multiple network switch modules have memory interfaces configured for transferring packet data to respective local buffer memories via local memory controllers. The local memory controllers are connected to each other to form a signal memory pool for transfer among each other data units of data frames received from different network switch modules. Each of the controllers are also connected to a corresponding local buffer memory and either write received data units in the corresponding local buffer memory or transfer the received data units to other controllers that, in turn, write the data units in their corresponding local buffer memory. The local memory controllers transfer and write and read the data units according to a prescribed sequence, optimizing memory bandwidth by concurrently executing a prescribed number of successive memory writes or memory reads.
Abstract: The present invention, in one embodiment, relates to a process for fabricating a semiconductor device that is less susceptible to performance degradation caused by hydrogen contamination. The method includes the steps for removing unwanted hydrogen bonds by exposing the hydrogen bonds to ultraviolet radiation sufficient to break the bond and annealing in an atmosphere comprising at least one gas having at least one atom capable of forming bonds that replace the hydrogen bonds.
Abstract: A network is described for providing estimates of the current time. The network includes multiple computer systems each configured to provide an estimate of the current time in response to a received request. The computer systems are logically arranged to form a hierarchical structure, wherein the hierarchical structure includes multiple levels ranked with respect to one another. Each of the computer systems is assigned one of multiple levels of trust, and occupies one of the levels of the hierarchical structure dependent upon the assigned level of trust. The level of trust assigned to a given computer system is dependent upon a timekeeping dependability of the given computer system. The assigned level of trust may also be dependent upon a timekeeping security of the given computer system, where the timekeeping security is dependent upon a tamper resistance of the time clock of the given computer system. Methods for delegating a level of trust to a new computer system (i.e.
Abstract: A system includes a main memory device which stores information for translating a virtual address into a physical address in response to one of a plurality of processing devices. A memory control/interface device is coupled to the main memory device. The memory control/interface device, which may access the information stored in the main memory device, has a separate translation look-aside buffer for each processing device. Each translation look-aside buffer can buffer the information for use in translating in response to the respective processing device.
Type:
Grant
Filed:
January 4, 2000
Date of Patent:
May 25, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
John C. Peck, Jr., Sridhar P. Subramanian, Scott Waldron
Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes a network switch port having a filter (i.e., a packet classifier module) configured for evaluating an incoming data packet on an instantaneous basis. The filter performs simultaneous comparisons between the incoming data stream of the data packet and multiple templates configured for identifying respective data attributes. Each template is composed of a plurality of min terms, wherein each min term specifies a prescribed comparison operation within a selected data byte of the incoming data packet. The templates may be programmed by a user and stored in an internal min term memory. Hence, the filter can identify selected attributes, such as whether the layer 2 packet includes an SNMP packet or an HTTP packet, regardless of whether the IP frame is in IPv4 format or IPv6 format.
Abstract: A host channel adapter is configured for servicing a work notification, supplied by a host process to an assigned destination address accessable by the host channel adapter, based on matching the assigned destination address with a stored notification address from one of a plurality of queue pair context entries stored within the host channel adapter. The host channel adapter receives a queue pair context entry including a notification address, based on creation of a corresponding queue pair for a host process. The queue pair enables the host process to post a work descriptor and output a work notification to the host channel adapter by writing the work notification to an assigned destination address. The host channel adapter matches the assigned destination address with a stored notification address, and services the work descriptor based on the corresponding queue pair attributes specified in the identified queue pair context entry.
Abstract: A mask generator circuit includes at least first and second mask generator circuits coupled to receive most significant and least significant sections of the pointer and to generate masks therefrom, and a plurality of circuits each configured to generate a region of the output mask from the mask generator circuit. The mask generated from the most significant bits section of the pointer (the most significant bits (MSB) mask) includes bits corresponding to various regions of the output mask. The plurality of circuits receive the MSB mask and the least significant bits (LSB) mask generated from the least significant bits section of the pointer and generate the output mask therefrom.
Abstract: In a memory device, a substrate has a plurality of source/drain regions in the substrate. Between the source/drain regions are trenches filled with oxide. Individual bit lines in the form of conductive regions are provided in the substrate, each bit line being under and running along the oxide in a trench. Each bit line connects to source/drain regions by means of connecting conductive regions extending from that bit line to source/drain regions.
Abstract: A method of manufacturing a semiconductor device includes forming a buried insulator layer of a semiconductor-on-insulator (SOI) wafer with a dopant material, such as boron, therein. The insulator material with the dopant material may be formed by a number of methods, for example by thermal oxidation of a semiconductor wafer in the presence of an atmosphere containing the dopant material, by co-deposition of the insulator material and the dopant material, or by co-implantation of an insulator material and the dopant material. The dopant material may be the same as a dopant material in at least a region (e.g., a source, drain, or channel region) of a semiconductor material layer which overlies the insulator layer. The dopant material in the buried insulator layer may advantageously reduce the tendency of dopant material to migrate from the overlying material to the insulator layer, such as during manufacturing operations involving heating.
Abstract: A method for identifying faulty wafers includes processing a set of wafers in a tool; collecting tool state information during the processing of the set of wafers; generating a tool state information baseline; comparing the tool state information for each wafer to the tool state information baseline to identify any wafers with outlying tool state information; and designating a particular wafer in the set as suspect in response to identifying outlying tool state information for the particular wafer. A processing line includes a tool adapted to process a set of wafers, and a process controller.
Type:
Grant
Filed:
March 22, 2001
Date of Patent:
May 18, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Terrence J. Riley, Qingsu Wang, Glen W. Scheid, Kent F. Knox
Abstract: A method of quantizing multiple input values in parallel using SIMD instructions is disclosed. In one embodiment, the method comprises (1) receiving a set of input values Xi; (2) operating on the set of input values to produce a set of binary mask values Ki that are related to the input values Xi by Ki=−1 if Xi>0, and Ki=0 if Xi<0; (3) adding half of a quantization step Q to the input values Xi to obtain sum values; (4) subtracting half of a quantization step Q to the input values Xi to obtain difference values; (5) using the binary mask values to screen out sum values calculated from negative input values; (6) using a complementary binary mask to screen out difference values calculated from positive input values; and (7) combining the screened sum and difference values to determine prequantization values Yi that can be expressed Yi=Xi+Q/2 if Xi>0, and Yi=Xi−Q/2 if Xi≦0.
Abstract: The present invention is generally directed to a semiconductor device formed over a multiple thickness buried oxide layer, and various methods of making same. In one illustrative embodiment, the device comprises a bulk substrate, a multiple thickness buried oxide layer formed above the bulk substrate, and an active layer formed above the multiple thickness buried oxide layer, the semiconductor device being formed in the active layer above the multiple thickness buried oxide layer. In some embodiments, the multiple thickness buried oxide layer is comprised of a first section positioned between two second sections, the first section having a thickness that is less than the thickness of the second sections.
Type:
Grant
Filed:
March 28, 2002
Date of Patent:
May 18, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Mark B. Fuselier, Derick J. Wristers, Andy C. Wei
Abstract: A method and system for determining an operating voltage for a semiconductor device. A first plurality of lifetimes may be determined for a first plurality of semiconductor device where the polysilicon lines in each of the first plurality of semiconductor devices have the same total area but different peripheral lengths. A second plurality of lifetimes may be determined for a second plurality of semiconductor devices where the polysilicon lines in each of the second semiconductor device have the same peripheral length but different total areas. Further, the STI structures (used to separate one or more active areas) in each of the second plurality of semiconductor devices may have the same length as the STI structures (used to separate one or more active areas) in each of the first plurality of semiconductor devices. The operating voltage may be determined based on the first and second plurality of lifetimes.
Abstract: A method for controlling a photolithography process includes forming a first layer on a selected wafer. A first overlay error associated with the first layer is measured. At least one parameter in an operating recipe for performing a photolithography process on a second layer formed on the first wafer is determined based on at least the first overlay error measurement. A processing line includes a photolithography stepper, and overlay metrology tool, and a controller. The photolithography stepper is configured to process wafers in accordance with an operating recipe. The overlay metrology tool is configured to measure overlay errors associated with the processing of the wafers in the photolithography stepper.
Type:
Grant
Filed:
December 17, 2001
Date of Patent:
May 18, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Christopher A. Bode, Alexander J. Pasadyn
Abstract: A method of utilizing a multilayer photoresist to form contact holes and/or conductors utilizing a dual damascene process includes utilizing layered photoresists. A contact in a conductive line can be formed in a single deposition step or in a two-stage deposition step. Image layers can remain as part of the interconnect structure or be removed by a polishing technique. The process can be utilized for any conductive structures provided above a substrate of an integrated circuit.
Type:
Grant
Filed:
June 19, 2001
Date of Patent:
May 18, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Ramkumar Subramanian, Christopher F. Lyons, Marina V. Plat, Scott A. Bell
Abstract: According to one exemplary embodiment, a structure comprises a first bit line and a second bit line. The structure further comprises a first memory cell situated over the first bit line, where the first memory cell comprises a first ONO stack segment, and where the first ONO stack segment is situated between the first bit line and a word line. The structure further comprises a second memory cell situated over the second bit line, where the second memory cell comprises a second ONO stack segment, where the second ONO stack segment is situated between the second bit line and the word line, and where the first ONO stack segment is separated from the second ONO stack segment by a gap. The first memory cell and the second memory cell may each be capable, for example, of storing two independent data bits.
Abstract: A method for scheduling activities in a manufacturing system includes defining a plurality of observed states associated with the manufacturing system. State estimates are generated for the observed states. Uncertainty values for the state estimates are generated. A plurality of candidate schedules for performing activities in the manufacturing system is identified. Changes to the uncertainty values are predicted based on the candidate schedules. One of the candidate schedules is selected based on the predicted changes to the uncertainty values.
Abstract: A non-volatile memory device includes a semiconductor substrate having first and second bitlines buried therein. The first bitline serves as a source terminal and the second bitline serves as a drain terminal. An oxide-nitride-oxide (ONO) stack is formed over the substrate. The ONO stack includes a charge storing layer having at least four charge storing cells therein. A pair of complementary conductive regions are disposed on opposite sides of the ONO stack extending in a direction perpendicular to the first and second bitlines. A wordline, which serves as a gate electrode, is disposed above the ONO stack and laterally between the first and second complementary conductive regions.
Type:
Grant
Filed:
December 10, 2002
Date of Patent:
May 11, 2004
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Ashot Melik-Martirosian, Sameer S. Haddad, Mark W. Randolph
Abstract: A method of indirect addressing involves use of a bank select register and a bank of multiple directly-accessible registers to indirectly access registers of a memory device. Bank select data is written to the bank control register, specifying a bank of registers to be indirectly accessed. Read and/or write operations are then performed, for example, reading data from the specified bank of registers and transferring it to the bank of directly-accessible registers, or writing data to the bank of directly-accessible registers from an external source, and transferring the data to the registers of the specified bank.
Abstract: CMOS devices with balanced drive currents are formed with a PMOS transistor based on SiGe and a deposited high-k gate dielectric. Embodiments including forming a composite substrate comprising a layer of strained Si on a layer of SiGe, forming isolation regions defining a PMOS region and an NMOS region, forming a thermal oxide layer on the strained Si layer, selectively removing the thermal oxide layer and strained Si layer from the PMOS region, depositing a layer of high-k material on the layer of SiGe in the PMOS region and then forming gate electrodes in the PMOS and NMOS regions.