Abstract: A host controller such as a USB host controller in a southbridge, and a corresponding operation method are provided. The host controller comprises a descriptor fetch unit that is adapted to send out requests for descriptors and receive descriptors in reply to the requests. The descriptors are data structures for describing attributes of the data transfer to and from the devices controlled by the host controller. The host controller further comprises a descriptor cache that is adapted to store prefetched descriptors. The descriptor cache is further adapted to store individual replacement control values for at least a part of the stored prefetched descriptors. The host controller is arranged to replace a stored prefetched descriptor in the descriptor cache by a newly prefetched descriptor based on the replacement control value that is associated with the stored prefetched descriptor. The replacement technique may improve the overall efficiency of the host controller operation.

Abstract: Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are formed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with xenon gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.

Abstract: A method for forming silicide contacts includes forming a layer on silicon-containing active device regions such as source, drain, and gate regions. The layer contains a metal that is capable of forming one or more metal silicides and a material that is soluble in a first metal silicide but not soluble in a second metal silicide, or is more soluble in the first metal silicide than in the second metal silicide. The layer may be formed by vapor deposition methods such as physical vapor deposition, chemical vapor deposition, evaporation, laser ablation, or other deposition method. A method for forming silicide contacts includes forming a metal layer, then implanting the metal layer and/or underlying silicon layer with a material such as that described above. The material may be implanted in the silicon layer prior to formation of the metal layer. Contacts formed include a first metal silicide and a material that is more soluble in a first metal silicide than in a second metal silicide.

Abstract: The present invention provides for a method and an apparatus for controlling plasma photoresist removal processes. At least one manufacturing run of semiconductor devices is processed. Environmental data is acquired in response to processing the semiconductor devices. Metrology data is acquired in response to processing the semiconductor devices. The method further comprises performing residual gas analysis based upon the acquired environmental data and the acquired metrology data.

Abstract: The protocol of a multi-pipe interconnection bus includes the ability to send a non-addressed read or write transaction request over one of the pipes of a multiple-pipe computer interconnect bus. The multiple pipes carry transactions on a packet multiplexed basis. The transaction request is sent over one of the pipes from a source to a target and includes a non-addressed transaction command. The transaction is performed in a predetermined location in response to the non-addressed transaction command. A transaction response is returned upon completion of the transaction.

Abstract: In a process for forming a photoresist mask, a photoresist layer is applied to a substrate. A silyated layer is formed in the photoresist layer. The features of the silyated area correspond to the features of a photoresist mask to be formed. The photoresist layer is then etched to form a photoresist base beneath the silyated area. The photoresist base is etched to remove material from its sides such that it becomes narrower than the silyated area. The silyated area is then removed, leaving a photoresist mask on the substrate.

Abstract: The reliability and electromigration resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer with at least one alloying element for the metal of the feature, and then uniformly diffusing at least a minimum amount of the at least one alloying element of the at least one thin layer for a predetermined minimum depth below the upper surface of the features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer.

Abstract: Interconnects to an underlying Cu feature are formed with improved reliability by replacing a portion of the capping layer in the bottom of an opening in an overlying dielectric layer, e.g., an ILD, with a barrier material, such as Ta or TaN. During Ar sputter etching to round the ILD corners, the exposed barrier layer portion is removed and redeposited to form a liner on the side surfaces of the dielectric layer defining the opening, thereby avoiding Cu redeposition on, and/or penetration through, the side surfaces of the dielectric layer.

Abstract: A multilayer electrically conductive stack is formed in a semiconductor device prior to one step of photolithography. In this multilayer electrically conductive stack, alternate layers of the stack contain materials that differ in their refractive indices. In one instance, the electrically conductive stack can serve as an anti-reflective coating in the photolithographical processing. As the electrically conductive stack has chemical and electrical properties similar to those of an underlying device structures, removal of the multilayer stack after the photolithographical step is not required. In one instance, the electrically conductive stack can be used to form a gate structure or an interconnect structure. In an embodiment of the invention, alternate layers consist of Si1−xGex and Si, respectively.

Abstract: A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice strain; (b) forming a device structure in the semiconductor substrate by a process comprising forming at least one amorphous region in at least one portion of the strained lattice semiconductor layer; and (c) thermal annealing at a minimum temperature sufficient to effect epitaxial re-crystallization of the at least one amorphous region to re-form a strained lattice semiconductor layer having substantially the pre-selected amount of lattice strain, whereby strain relaxation of the strained lattice semiconductor arising from thermal annealing is substantially eliminated or minimized.

Abstract: A network repeater having a plurality of repeater ports selectively establishes links with remote nodes at one of two data rates based on the capabilities of the remote network node and a determined link integrity. A network repeater establishes a link with a network node using auto-negotiation techniques to establish a 100 Mb/s link. The network repeater than monitors the link for symbol errors, and determines an integrity of the link based on a detected number of symbol errors relative to a prescribed threshold in a dual-counter configuration. If the detected number of symbol errors counted by the first counter reaches a first threshold within a first number of received symbols, the second counter is incremented and the first counter reset.

Abstract: A method for forming a uniformly planarized structured in a semiconductor wafer forms metal structures on a substrate layer with spaces between the structures. The top surfaces of the metal structures lie within a common plane. Dielectric material is deposited on the layer, the metal structures and in the spaces. The dielectric layer is first etched so that the dielectric material in the spaces is below the common plane. Additional dielectric material is then deposited on the layer, the metal structures and in the spaces. The dielectric layer is then subjected to a second etching. Further deposition and etching steps are performed until the top of the dielectric layer and the top surfaces of the metal structures have a common, substantially uniform planarization.

Abstract: Various methods and apparatus for polishing semiconductor workpieces using electrochemically generated species are disclosed. In one aspect, a method of processing is provided that includes contacting a semiconductor workpiece to a solution, electrochemically generating a chemical species in the solution, and polishing the semiconductor workpiece with the aid of the solution.

Abstract: A method (300) of fabricating a semiconductor device. An oxide layer (220) is produced on a sidewall (211) of a stacked gate (210) and over a shallow trench (212) adjacent to the stacked gate. The thickness of the oxide layer is sufficient to withstand a subsequent etch. A first layer (222) of material is deposited over the oxide layer. In a first etch, the first layer is reduced to a first thickness along the sidewall. Because the oxide layer has a depth sufficient to withstand the first etch, the oxide layer serves as a protective layer for the shallow trench during the first etch. Accordingly, a protective liner layer does not need to be deposited in addition to the oxide layer.

Abstract: A method of cycling dual bit flash memory arrays having a plurality of dual bit flash memory cells arranged in a plurality of sectors with each sector having an associated reference array that have dual bit flash memory cells that are cycled with the plurality of dual bit flash memory cells in the sectors. The dual bit flash memory cells in the associated reference array are then programmed.

Abstract: A system and method is provided for applying a developer to a photoresist material layer disposed on a semiconductor substrate. The developer system and method employ a developer plate having a plurality of a application apertures for dispensing developer and a plurality of exit apertures for allowing excess developer to be removed from between the developer plate and the photoresist material layer. Preferably, the developer plate has a bottom surface with a shape that is similar to the wafer. The developer plate is disposed above the wafer and substantially and/or completely surrounds the top surface of the wafer during application of the developer. A small gap is formed between the wafer and the bottom surface of the developer plate. The wafer and the developer plate form a parallel plate pair, such that the gap can be made small enough so that the developer fluid quickly fills the gap with excess developer exiting through the exit apertures.

Abstract: A mask generation method can enhance clear field phase shift masks using a chrome border around phase 180 regions. An exemplary method involves identifying edges of a 180 degree phase pattern, expanding these edges, and merging the expansions with chrome. An alternative method involves oversizing and undersizing phase 180 data, taking the difference, and merging the difference with chrome. The chrome region on the phase mask can improve mask generation by allowing the chrome on the mask to fully define the quartz etch.

Abstract: A method of fabricating an integrated circuit can include forming a barrier layer along lateral side walls and a bottom of a via aperture, forming a seed layer proximate and conformal to the barrier layer, and forming an implanted layer proximate and conformal to the barrier layer and the seed layer. The via aperture is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer.

Abstract: A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

Abstract: The reliability and electromigration life-time of planarized metallization features, e.g., copper, inlaid in the surface of a layer of dielectric material, are enhanced by a chemical vapor deposition process for depositing a passivation layer over the metallization patterns which comprises maintaining on the upper surfaces of the metallization features, at or below a first temperature, an inhibiting film previously deposited thereon. The inhibiting film substantially inhibits oxide layer formation on the surface of the metallization features below the first temperature. Passivation layer deposition occurs at a second temperature higher than the first temperature such that the time interval between removal of the inhibiting film and formation of the passivation layer is short enough to substantially inhibit the formation of oxides on the surface of the metal feature.