Abstract: A wireless local area network transceiver, an integrated circuit chip, a PLL (Phase Locked Loop) device and a method are provided that may reduce influences of switching noise. The frequency of an output signal of the PLL device is divided in a prescaler of the PLL device by a prescaler factor. The prescaler is operable in at least two modes with each mode having assigned a different prescaler factor. An accumulator is implemented in the PLL circuit for generating a mode switching signal for changing the mode of the prescaler. The generation of the mode switching signal is done by storing an accumulator value and processing a modulus function for updating the accumulator value. The provided technique may allow for reducing disturbances caused by switching the mode of the prescaler in the PLL circuit.

Abstract: A computer system may include multiple processing nodes, one or more of which may be coupled to separate memories which may form a distributed memory system. The processing nodes may include caches, and the computer system may maintain coherency between the caches and the distributed memory system. Particularly, the computer system may implement a flexible probe command/response routing scheme. The scheme may employ an indication within the probe command which identifies a receiving node to receive the probe responses. For example, probe commands indicating that the target or the source of transaction should receive probe responses corresponding to the transaction may be included. Probe commands may specify the source of the transaction as the receiving node for read transactions (such that dirty data is delivered to the source node from the node storing the dirty data).

Abstract: A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning.

Abstract: The invention provides systems and methods for controlling resist baking processes, such as PEB of chemically amplified photoresists. A system of the invention provides a baking plate through which hot fluids and cold fluids may be alternately circulated. The system takes measurements relating to temperature of the baking plate, temperature of the resist, and/or extent of the baking process. Using this data, the system controls the baking temperature and/or the overall extent of the baking process through control over the flow of hot and cold fluids. By alternating between hot and cold fluid circulation, systems of the invention provide rapidly responsive temperature control and/or abrupt termination of baking. Control over the baking process is further increased by implementing flow and process control separately over each of a plurality of different portions of a baking plate.

Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and forming a gate structure over a channel portion of the fin structure. The method may also include forming a sacrificial oxide layer around the gate structure and removing the gate structure to define a gate recess within the sacrificial oxide layer. A metal gate may be formed in the gate recess, and the sacrificial oxide layer may be removed.

Abstract: A cache is coupled to receive an input address and a corresponding way prediction. The cache provides output bytes in response to the predicted way (instead of, performing tag comparisons to select the output bytes). Furthermore, a tag may be read from the predicted way and only partial tags are read from the non-predicted ways. The tag is compared to the tag portion of the input address, and the partial tags are compared to a corresponding partial tag portion of the input address. If the tag matches the tag portion of the input address, a hit in the predicted way is detected and the bytes provided in response to the predicted way are correct. If the tag does not match the tag portion of the input address, a miss in the predicted way is detected. If none of the partial tags match the corresponding partial tag portion of the input address, a miss in the cache is determined.

Abstract: A system and method are provided for optimizing the translation of virtual addresses into physical addresses for a graphics address remapping table (GART). In the system and method, a translation look-aside buffer cache has a plurality of translation look-aside buffer entries. Each translation look-aside buffer entry is operable to buffer information which may be accessed for use in translating a virtual address into a physical address. A least recently used pointer circuit is operable to point to a translation look-aside buffer entry buffering information least recently used in the translation look-aside buffer cache. During operation, updates to the least recently used pointer circuit may be pipelined with corresponding accesses to the translation look-aside buffer cache.

Abstract: An apparatus and method for generating 64 bit displacement and immediate values. In a given processor architecture such as the x86 architecture, instructions may conform to a specified instruction format. The instruction format can include a displacement field and an immediate field. The displacement field can include a displacement value of up to 32 bits and the immediate field can include an immediate value of up to 32 bits. In order to generate 64 bit displacement and immediate values, the 32 bit value from the displacement field of an instruction and the 32 bit value from the immediate field of the instruction may be concatenated to generate a 64 bit concatenated value. The concatenated value may be used by an execution core as a 64 bit displacement or immediate value as specified by the instruction.

Abstract: One aspect of the present invention relates to a method of dual damascene processing, involving forming a plurality of via openings in the insulation structure containing a single layer of a dielectric material; and simultaneously (i) forming a plurality of trenches in the insulation structure, each trench positioned along the substantially straight line of a group of via openings, and (ii) monitoring the formation of trenches using a scatterometry system to determine trench depth, and terminating forming the trenches when a desired trench depth is attained.

Abstract: According to an example embodiment of the present invention, a defect detection approach involves detecting the existence of defects in an integrated circuit as a function of at least one applied energy source. In response to energy that is applied to the integrated circuit, response signals are detected. A parameter including information such as amplitude, frequency, phase, or a spectrum is developed for a reference integrated circuit device and then compared to the detected response signal. The deviation in the response and reference signals, and the type of energy source used, are correlated to a particular defect in the device.

Abstract: A thin silicon nitride layer is deposited at an ultra low deposition rate by PECVD by reducing the NH3 flow rate and/or reducing the SiH4 flow rate. Embodiments include depositing a thin layer of silicon nitride, e.g., 100 Å or less, on a thin silicon oxide liner over a gate electrode, at an NH3 flow rate of 100 to 800 sccm, a SiH4 flow rate of 50 to 100 sccm and a reduced pressure of 0.8 to 1.8 Torr. Embodiments of the present invention further include depositing the silicon nitride layer in multiple deposition stages, e.g., depositing the silicon nitride layer in five deposition stages of 20 Å each.

Abstract: The present invention provides systems and methods that facilitate formation and use of organic memory devices. An electroless plating process is employed that operates at relatively low temperatures and without employing electrical current. The electroless process is utilized to form conductive layers, such as electrodes and the like, from conductive materials. The process includes depositing an activation compound on selected areas and then applying a chemical solution. The chemical solution contains metal ions. Then, a chemical reaction occurs reducing the metal ions and thereby plating the metal ions and forming a conductive layer. Specifically, the electroless process can be employed to form a top electrode of an organic memory device.

Abstract: A method includes processing a plurality of workpieces in accordance with an operating recipe. A defectivity metric is determined based on the operating recipe. A sampling plan for measuring a characteristic of selected workpieces processed using the operating recipe is determined based on the defectivity metric. A manufacturing system includes a process tool and a sampling controller. The process tool is configured to process a plurality of workpieces in accordance with an operating recipe. The sampling controller is configured to determine a defectivity metric based on the operating recipe and determine a sampling plan for measuring a characteristic of selected workpieces processed using the operating recipe based on the defectivity metric.

Abstract: A method for fabricating a semiconductor device, involving: forming a gate stack on a substrate; depositing a material layer on the gate stack; etching the material layer, thereby forming a dielectric capsulate layer on the gate stack; forming a pair of shallow source/drain extensions in a first region of the substrate by implanting a plurality of first dopant ions at a tilt angle with a horizontal offset defined by a thickness of the dielectric capsulate layer; and forming at least one spacer on the dielectric capsulate layer; forming deep source/drain contact junctions in a second region of the substrate by vertically implanting a plurality of second dopant ions below the first region with no tilt and with a horizontal offset defined by a thickness of the at least one spacer.

Abstract: A silicon-on-insulator (SOI) device with a strained silicon film has a substrate, and a buried oxide layer on the substrate. Silicon islands are formed on the buried oxide layer, the silicon islands being separated from each other by gaps. The buried oxide layers has recesses directly under the gaps. A material fills the recesses and the gaps, this material being different from the material forming the buried oxide layer. The material induces a net amount of strain in the silicon islands, thereby modifying the electrical properties of carriers in the silicon film and improving device performance.

Abstract: The invention, in its various aspects and embodiments, is a method and apparatus for controlling the operation of a multi-chamber process tool in a semiconductor fabrication process. The method comprises setting a plurality of operation parameters for the conduct of a predetermined operation in each of a plurality of process chambers in a multi-chamber process tool; performing the predetermined operation in each of the process chambers; examining a physical characteristic of a processed wafer from each of the process chambers; determining from the examined physical characteristics whether the operating conditions in each of the process chambers match; and resetting at least one operating parameter so that the operating conditions in each of the process chambers will match. The apparatus comprises a processing tool, a review station, and a tool controller. The processing tool includes a plurality of process chambers and an operation controller.

Abstract: There is disclosed a processing system comprising: 1) a first data processor comprising a unified memory architecture for receiving memory access requests from an external bus coupled to the first data processor; 2) a memory coupled to the first data processor and controlled by the unified memory architecture, the memory storing a first plurality of instructions executable by the first data processor; and 3) a second data processor coupled to the external bus and capable of sending the memory access requests to the first data processor, wherein the memory access requests access data used by the second data processor stored in the memory.

Abstract: An integrated reliability monitor that automatically tests a memory device until a threshold number of errors has been detected. The integrated reliability monitor eliminates the need for sophisticated external test equipment by automatically testing the memory cells in the memory array and providing the results. An optional programmable registers may store the error threshold value. The programmable registers may also store a time-out value or the reliability monitor may be externally interrupted.

Abstract: The present invention is directed to an integrated circuit having an increased gate coupling capacitance. The integrated circuit includes a substrate having a surface, the substrate having a trench extending below the surface. A trench fill material is disposed in the trench and has a portion extending above the surface. A first conductive layer is adjacent the trench fill material and has a portion extending over the portion of the insulative material. An insulative layer is adjacent the first conductive layer and a second conductive layer is adjacent the insulative layer. The present invention further is directed to a method of fabricating an integrated circuit on a substrate including the steps of forming a trench in the substrate, the trench extending below a surface of the substrate; providing a trench fill material in the trench such that the trench fill material extends above the surface of the substrate; and providing a first conductive layer over at least a portion of the trench fill material.

Abstract: A carrier member is provided that has a plurality of landing pads thereon where at least one of the landing pads has a depression therein to hold at least one solder terminal of a device to be mounted thereto. Embodiments include a ceramic or a bismaleimide-triazine epoxy laminate carrier having an array of landing pads formed by depositing a eutectic solder, where each landing pad in the comer of the array has a depression therein.