Abstract: Various methods of determining ion implant dosage are disclosed. In one aspect, a method of processing a semiconductor workpiece that has a device region and an inactive region is provided. A first mask is formed on a first portion of the inactive region. A first implant of ions is performed on the device region and the first mask. A secondary ion mass spectrometry analysis of the first portion of the first mask is performed to determine a composition thereof relative to a standard composition. A dose for the first implant is determined based upon the secondary ion mass spectrometry analysis of the first portion of the first mask. The first implant dose is compared with a prescribed dose for the first implant to determine if a second implant is necessary to achieve the prescribed dose, and if so, an appropriate make-up dose for the second implant.

Abstract: A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a second etch top layer, a dielectric layer and an opening extending through the dielectric layer, the first and second etch stop layers, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The second etch stop layer is disposed over the first diffusion barrier layer, and the first etch stop layer is disposed on the second etch stop layer with a first interface therebetween. The dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer and the barrier diffusion layer can be formed from silicon nitride, and the second etch stop layer can be formed from silicon oxide.

Abstract: A network appliance with a simplified network transmitter architecture includes a measurement/detection circuit for detecting a condition and generating a report signal corresponding to the measured or detected condition. A transmitter selects one of a plurality of condition reporting transmission frames corresponding to the measured or detected transmission and transmits the condition reporting transmission frame to a remote monitoring device across a network.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network includes a network switch port having a filter configured for evaluating an incoming data packet. The filter includes a min term memory configured for storing min term values. Each min term value is stored based on a location of a corresponding selected byte of the incoming data packet for comparison. Each min term is stored as a table entry having an expression portion specifying a corresponding comparison operation and a template identifier field that specifies templates that use the corresponding min term. The template identifier field includes an equation identifier. A min term generator is configured for simultaneously comparing a received byte of the incoming data packet with the min terms that correspond to the received byte and generates respective min term comparison results.

Abstract: A method for determining thickness of a process layer includes providing a wafer having a grating structure and a process layer formed over the grating structure; illuminating at least a portion of the process layer and the grating structure with a light source; measuring light reflected from the illuminated portion of the grating structure and the process layer to generate a reflection profile; and determining a thickness of the process layer based on the reflection profile. A processing line includes a metrology tool having a light source, a detector, and a data processing unit. The metrology tool is adapted to receive a wafer having a grating structure and a process layer formed over the grating structure. The light source is adapted to illuminate at least a portion of the process layer and the grating structure. The detector is adapted to measure light reflected from the illuminated portion of the grating structure and the process layer to generate a reflection profile.

Abstract: A method of fabricating an integrated circuit includes forming a barrier layer along lateral side walls and a bottom of a via aperture and providing a ternary copper alloy via material in the via aperture to form a via. The via aperture is configured to receive the ternary copper alloy via material and electrically connect a first conductive layer and a second conductive layer. The ternary copper alloy via material helps the via to have a lower resistance and an increased grain size with staffed grain boundaries.

Abstract: A semiconductor-on-insulator (SOI) device includes a thermoelectric cooler on a back side of the device. The thermoelectric cooler is formed on a thinned portion of a deep bulk semiconductor layer of the SOI device. The thermoelectric device includes a plurality of pairs of opposite conductivity semiconductor material blocks formed on a metal layer deposited on the thinned portion. The thinning of the thinned portion may be accomplished in multiple etching steps of the deep silicon layer, such as a fast etching down to an etch stop and a slower, more controlled etch to the desired thickness for the thinned portion.

Abstract: Various embodiments of a measurement tool are disclosed. In one aspect, a measurement tool is provided that includes a frame that has a first member. A second member is provided that is moveable relative to the first member along a first axis and a second axis. The first and second members have first and second cooperating structures engageable to enable the second member to be moved downward along the second axis to a preselected elevation when the second member is moved to a preselected position along the first axis. The movement of the second member along the first axis is constrained when the second member is moved to the preselected elevation. A meter is coupled to the second member for measuring feature heights. The meter has a contact surface that contacts the feature when the second member is moved to the preselected elevation. The tool provides for non-destructive probe card pin height measurement.

Abstract: A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions. The metal gate electrode is aligned using a polysilicon alignment structure, which permits high temperature processing before the metal is deposited.

Abstract: A method and arrangement for testing different types of external memories that can be coupled to a network interface controller. The network interface controller interprets the results of the memory test differently in accordance with the memory type. A fail state indicator is used by test controller to indicate the proper offset to add or subtract to a test address to calculate the actual failing memory location.

Abstract: According to the present invention, a method for inserting scan hardware into Integrated Circuits (IC) such as microcontrollers is disclosed. Custom scripts used by electronic design automation (EDA) tools are configured to accommodate those microcontroller designs that operate with multiple clocks and legacy cores. Furthermore, according to the present invention, custom script are used to provide buffering circuits to drive the scan hardware.

Abstract: The surface area of silicon lines which receives a silicide portion is increased to decrease the line resistance in narrow polysilicon lines, such as gate electrodes. Sidewall spacers are formed such that an upper portion of the line sidewall is exposed so as to react with a refractory metal to form a low resistance silicide. The upper portion may be exposed by overetching the dielectric layer deposited to form the sidewall spacers.

Abstract: A technique in which a boundary region is added to the outside parallel edge of phase zero (0) pattern defining polygons. This technique can reduce the need for optical proximity correction (OPC) and improve the manufacturability and patterning process window for integrated circuits. The technique can also set the width of both phase 0 and phase 180 polygons to specific sizes, making OPC easier to assign.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes network switch ports, each including a policy filter configured for obtaining layer 3 and layer 4 information from a received layer 2 frame. The layer 3 information and the layer 4 information are used to determine a policy identifier that specifies a layer 3 switching operation to be performed on the received layer 2 frame. Each network switch port also includes a policy cache that caches portions of the layer 3 information and the corresponding policy identifier. The policy filter and the policy cache are then simultaneously searched for subsequent layer 3 frames to find the appropriate policy; if the appropriate policy is located in the policy cache, the searching operation is completed, enabling the network switch port resources to begin searching operations for another packet.

Abstract: A process for fabrication of a semiconductor device including a modified ONO structure, including forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric material on the first oxide layer; and forming a top oxide layer on the layer comprising a high-K dielectric material. The semiconductor device may be, e.g., a MIRRORBIT™ two-bit EEPROM device or a floating gate flash device including a modified ONO structure.

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed in a high temperature process after the trench is filled with an insulative material. The insulative material is provided in a low temperature process.

Abstract: A method for controlling the flow of wafers through a process flow includes monitoring operating states of a plurality of processing tools adapted to process wafers; measuring a characteristic of a particular incoming wafer; identifying a particular processing tool having an operating state complimentary to the measured characteristic; and routing the particular incoming wafer to the particular processing tool for processing. A manufacturing system includes a plurality of processing tools adapted to process wafers and a process control server. The process control server is adapted to access metrology data related to a characteristic of a particular incoming wafer, identify a particular processing tool having an operating state complimentary to the characteristic, and route the particular incoming wafer to the particular processing tool for processing.

Abstract: A method is provided for compressing data. The method includes collecting data representative of a process. The method further includes scaling at least a portion of the collected data to generate mean values and mean-scaled values for the collected data. The method also includes calculating Scores from the mean-scaled values for the collected data using at most first, second, third and fourth Principal Components derived from a model using archived data sets and saving the Scores and the mean values.

Abstract: A method for producing an integrated circuit includes providing a diamond layer above a layer of conductive material. A cap layer is provided above the diamond layer and patterned to form a cap feature. The diamond layer is patterned according to the cap feature to form a mask, and at least a portion of the layer of conductive material is removed according to the mask.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. An interconnect cap is disposed over the conductor core and seed layer and is capped with a capping layer. The interconnect cap is preferably of an indium oxide compound.