Abstract: A method of fabricating a charge trapping dielectric memory cell array comprises exposing a first photoresist to a first illumination pattern from a first mask to pattern bit line regions in a core region of the wafer and to pattern alignment mark regions. The alignment mark regions may be in a scribe lane region of the wafer. An impurity is implanted into the wafer within the bit line regions and the alignment mark regions and an oxide is grown on the surface of the wafer in the scribe lane region to produce oxide protrusions within the alignment mark regions. A second photoresist is exposed to a second illumination pattern from a second mask to pattern word line regions within the core region of the wafer and utilizing surface height variations of the oxide protrusions to detect alignment between the second mask and the first mask.

Abstract: A network receiver is configured for receiving a modulated carrier signal representing a data frame from another network transceiver via a network medium, the modulated carrier signal may be either a pulse position modulated (PPM) carrier, a quadrature amplitude modulated (QAM) carrier, or a compatibility mode frame including both PPM and QAM portions. The network receiver is configured to select an A/D sampling clock frequency corresponding to the detected frame type.

Abstract: An asymmetric retrograde HALO Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) includes a semiconductor substrate. A gate is formed over the substrate, the gate defining a channel thereunder in the substrate having a source side and a drain side. A retrograde HALO doped area is formed in the source side of the channel using tilted ion implantation. A source and drain are formed in the substrate adjacent to the source and drain sides of the channel. The asymmetrical doping arrangement provides the specified level of off-state leakage current without decreasing saturation drive current and transconductance.

Abstract: A system for identifying wafers contained in a wafer carrier includes a wafer sorter. Each wafer includes a surface terminating in an edge and a plurality of sector identification codes disposed on the surface proximate the edge. The wafer sorter is adapted to scan at least a portion of a wafer extending from the carrier and to identify at least one of the sector identification codes on the wafer independent of the orientation of the wafer in the wafer carrier. A method for identifying wafers contained in a wafer carrier is provided. Each wafer includes a surface terminating in an edge and a plurality of sector identification codes disposed on the surface proximate the edge. The method includes scanning at least a portion of a wafer extending from the carrier and identifying at least one of the sector identification codes on the wafer independent of the orientation of the wafer in the wafer carrier.

Abstract: A method of manufacturing a semiconductor device etches a feature on a substrate in accordance with a photoresist mask. The photoresist mask is removed by plasma etching. Laser thermal annealing is performed to vaporize polymer residue created during the stripping of the photoresist mask, and to repair damage to the substrate.

Abstract: A method is provided for obtaining an accurate image of a two-dimensional junction profile of a semiconductor device. Embodiments include sectioning a sample to be analyzed through the active transistor, either at a 90° angle to the planar surface or at a desired angle, as by a focused ion beam (FIB) apparatus. The sectioned transistor can be analyzed directly on the exposed silicon, or the exposed silicon of the cross-section can be passivated with a thin film material such as silicon dioxide, or with an undoped semiconductor material such as silicon or germanium. The electrodes (i.e., source, gate, drain and substrate electrodes) of the sample active transistor are then connected so they can be individually electrically biased. The prepared sample is placed in a conventional voltage contrast SEM, and the electrodes are selectively biased to produce a voltage contrast while being imaged by the voltage contrast SEM, thereby resulting in detailed SEM images of the active regions and depletion spreads.

Abstract: A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces.

Abstract: An exemplary method of constructing an alternating phase-shifting mask is described. This method can include providing a vapor in a vapor chamber containing a mask blank, and applying a laser to selected areas of the mask blank to deposit material on the integrated circuit substrate. The material is configured to cause a 180° phase shift at the wavelengths the mask is designed for such as 248 nm, 193 nm or 157 nm.

Abstract: A system and method are provided for detecting latent defects in a mask or reticle, which defects may vary as a function of radiation at exposure wavelengths. By way of example, the mask or reticle is inspected, exposed to radiation at a specified wavelength, and then reinspected. A correlation between the inspection results before and after exposure provides an indication of exposure-related defects, which may include defect growth and/or formation of defects caused by the exposure. By way of further illustration, the combination of inspection and exposure of a mask or reticle may be implemented with respect to a pellicized mask or reticle so as to detect additional defects related to use of the pellicle with the mask or reticle.

Abstract: One aspect of the present invention relates to a method of cleaning a patterned photoresist clad structure involving the steps of contacting the patterned photoresist clad structure with an alcohol vapor comprising at least one compound having the Formula ROH, wherein R is a hydrocarbon group comprising from 4 to about 8 carbon atoms; condensing the alcohol vapor on the patterned photoresist clad structure; and removing the condensed alcohol vapor from the patterned photoresist clad structure. Another aspect of the present invention involves the use of an alcohol vapor having a boiling point from about 102° C. to about 175° C. Yet another aspect of the present invention involves the use of an alcohol vapor having a flash point from about 15° C. to about 80° C.

Abstract: An exemplary method of forming trench lines includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers on lateral sides of the ARC features; and etching trench lines using the spacers and ARC features as hard mask to define portions of the layer of material which are etched.

Abstract: A metal gate structure and method of forming the same employs an etch stop layer between a first metal layer, made of TiN, for example, and the metal gate formed of tungsten. The etch stop layer prevents overetching of the TiN during the etching of the tungsten in the formation of the metal gate. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum in the etch stop layer allows a thin etch stop layer to be used that provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.

Abstract: In one illustrative embodiment, the method comprises initiating a develop process on a layer of photoresist formed above a wafer, indicating an endpoint of the develop process, determining a duration of the endpoint develop process, and determining if the determined duration of the develop process is not within a preselected range. In another aspect, the present invention is directed to a system that comprises a develop station for performing a develop process on a layer of photoresist formed above a wafer, a develop endpoint detector for indicating an endpoint of the develop process, and a controller for determining if a duration of the develop process is not within a preselected range.

Abstract: For fabricating field effect transistors with a semiconductor substrate in SOI (semiconductor on insulator) technology, a first hardmask is formed on a first area of the semiconductor substrate, and a first dielectric forming dopant is implanted into a second area of the semiconductor substrate that is not covered by the first hardmask. The first hardmask is removed from the first area of the semiconductor substrate. A second hardmask is formed on the second area of the semiconductor substrate, and a second dielectric forming dopant is implanted into the first area of the semiconductor substrate that is not covered by the second hardmask. A thermal anneal is performed to form a first buried insulating structure from the second dielectric forming dopant reacting within the first area of the semiconductor substrate and to form a second buried insulating structure from the first dielectric forming dopant reacting within the second area of the semiconductor substrate.

Abstract: An exemplary embodiment relates to a method of using amorphous carbon in replacement gate integration processes. The method can include depositing an amorphous carbon layer above a substrate, patterning the amorphous carbon layer, depositing a dielectric layer over the patterned amorphous carbon layer, removing a portion of the deposited dielectric layer to expose a top of the patterned amorphous carbon layer, removing the patterned amorphous carbon layer leaving an aperture in the dielectric layer, and forming a metal gate in the aperture of the dielectric layer.

Abstract: A method includes measuring a characteristic of a workpiece at a plurality of locations. A uniformity profile is generated based on the characteristic measurements. At least one acceptable region of the workpiece is identified based on the uniformity profile. At least one unacceptable region of the workpiece is identified based on the uniformity profile. The uniformity profile is filtered to remove at least a portion of the characteristic measurements associated with the second unacceptable region. At least one parameter of an operating recipe for performing a process on the workpiece is determined based on the filtered uniformity profile.

Abstract: In a method and system for monitoring erase pulses applied on a sector of flash memory cells fabricated on a semiconductor substrate, a pulse counter and a pulse counter controller are fabricated on the semiconductor substrate. The pulse counter controller inputs a maximum number and outputs an indication of a sector fail if the flash memory cells of the sector do not pass erase verification with less than the maximum number of erase pulses applied on the sector during an erase verify BIST (Built-in-Self-Test) mode. In one example, the maximum number is a percentage of a diagonal total number of erase pulses needed to be applied on the sector until each flash memory cell at a diagonal location of the sector passes erase verification.

Abstract: A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from a material different than the first barrier layer, and the material of the first barrier layer can be selected from the group consisting of tantalum, titanium, tantalum nitride, titanium nitride, and tungsten nitride.

Abstract: For fabricating an interconnect structure within a dielectric material comprised of at least one dielectric reactant element, an interconnect opening formed within the dielectric material is filled with a conductive fill material comprised of first and second dopant elements that are different. A diffusion barrier material, that surrounds the conductive fill material, is formed from a reaction of the first dopant element and a dielectric reactant element. Also, a boundary material, that surrounds the conductive fill material, is formed from a reaction of the second dopant element and a dielectric reactant element. The boundary material prevents diffusion of a dielectric reactant element from the dielectric material into the conductive fill material.

Abstract: Semiconductor devices with highly reliable Cu interconnects exhibiting reduced resistance are formed by sequentially depositing a seedlayer by PVD, depositing a conformal seedlayer enhancement film by CVD, and then laser thermal annealing the seedlayer enhancement film in nitrogen to expel impurities, enhance film conductivity, reduce film stress, increase film density, and reduce film roughness. Embodiments include single and dual Cu damascene techniques formed in dielectric layers having a dielectric constant no greater than about 3.9.