Abstract: A mechanism for exception and interrupt handling in multithreaded multiprocessors is provided. The mechanism allows the handling of exceptions and interruptions in a multithreaded multiprocessor computer, while hiding the multiprocessor nature of the computer from the operating system. Generally, when an operating system is cognizant of the multiprocessor nature of a computer, additional overhead may be required when handling exceptions and interruptions. Due to the overhead involved in saving and restoring processing states, the performance of a processor may be significantly impacted. Additional circuitry is provided which allows the multiprocessor nature of the computer to be hidden from the operating system, while minimizing the overhead necessary for proper handling.

Abstract: A method and an apparatus for forming an under bump metallurgy layer over a contact pad area on an interconnect formed over a semiconductor substrate are provided which eliminate a pretreatment process for removing native oxide on the contact pad area prior to the deposition of the under bump metallurgy layer. In one embodiment, the removal of a cap layer which insulates the contact pad area and the deposition of the under bump metallurgy layer are carried out without leaving a vacuum environment.

Abstract: Several different systems and methods are described involving arbitration between asynchronous and isochronous data for access to a data transport resource (e.g., a bus or a memory controller). A first embodiment of a system (e.g., a computer system or a communication system) includes an arbiter coupled to the data transport resource, an asynchronous queue for storing asynchronous data, and an isochronous queue for storing isochronous data. The isochronous queue has a data level range divided into multiple portions. A number of memory locations within the isochronous queue may define the data level range of the isochronous queue. The arbiter arbitrates between the asynchronous queue and the isochronous queue for access to the data transport resource dependent upon the portion of the data level range in which a level of data resides within the isochronous queue. The level of data within the isochronous queue may be a number of memory locations between a write pointer and a read pointer.

Abstract: A processing line includes a processing tool, a metrology tool, a processing monitor, and a sampling controller. The processing tool is configured to process workpieces. The metrology tool is configured to measure an output characteristic of selected workpieces in accordance with a sampling plan. The processing monitor is configured to monitor the processing of at least one workpiece in the processing tool to generate a fingerprint and determine a processing metric based on the fingerprint. The sampling controller is configured to receive the processing metric and determine the sampling plan for the metrology tool based on the processing metric. A method for processing workpieces includes processing a plurality of workpieces in a processing tool. A characteristic of selected workpieces is measured in accordance with a sampling plan. The processing of at least one workpiece in the processing tool is monitored to generate a fingerprint. A processing metric is determined based on the fingerprint.

Abstract: A manufacturing method provides a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening provided therein. An barrier layer lines the opening and a seed layer is deposited to line the barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is annealed to form an annealed region, which securely bonds the seed layer to the barrier layer and prevents electromigration along the surface between the seed and barrier layers.

Abstract: The present invention provides for a geometrically shaped pouch and container system for use in the storage, handling and dispensing of liquid chemicals. This system will result in far greater liquid chemical utilization efficiencies.

Abstract: The present invention provides an alloy electroplating system for semiconductor wafers including a plating chamber connected by a circulating system to a plating solution reservoir. The semiconductor wafer is used as the cathode with an inert primary anode in the plating chamber. A plurality of consumable remote secondary anodes at different voltages in the plating solution reservoir provides the metal ions for alloy plating.

Abstract: A test structure includes a plurality of trenches and a plurality of columns defined in the trenches. A method for determining column dimensions includes providing a wafer having a test structure comprising a plurality of trenches and a plurality of columns defined in the trenches; illuminating at least a portion of the columns with a light source; measuring light reflected from the illuminated portion of the columns to generate a reflection profile; and determining a dimension of the columns based on the reflection profile. A metrology tool adapted to receive a wafer having a test structure comprising a plurality of trenches and a plurality of columns defined in the trenches includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the columns. The detector is adapted to measure light reflected from the illuminated portion of the columns to generate a reflection profile.

Abstract: A method and an apparatus for controlling a deposition process in a manufacturing process. A process recipe setting step is performed. A process run of semiconductor devices is performed based upon the process recipe. Metrology data relating to the process run of semiconductor dev determination is made whether production results are within a predetermined tolerance level, based upon the metrology data. Process recipe settings are modified in response to a determination that the production results are within a predetermined tolerance level, based upon the metrology data. A processing tool is capable of receiving at least one control input parameter and a metrology data acquisition unit is interfaced with the processing tool and is capable of acquiring metrology data from the processing tool.

Abstract: The present invention is directed to a method and a system for non-destructively, efficiently and accurately detecting asymmetry in the profile of a feature formed on a wafer during the process of semiconductor fabrication. The method encompasses directing a beam of light or radiation at a feature and detecting a reflected beam associated therewith. Data associated with the reflected beam is correlated with data associated with known feature profiles to ascertain profile characteristics associated with the feature of interest. Using the profile characteristics, an asymmetry of the feature is determined which is then used to generate feedback or feedforward process control data to compensate for or correct such asymmetry in subsequent processing.

Abstract: A method and system for eliminating post etch residues is disclosed. In one method embodiment, the present invention recites disposing a surface, having post etch residues adhered thereto, proximate to an electron beam source which generates electrons. The present method embodiment then recites bombarding the post etch residues with the electrons such that the post etch residues are removed from the surface to which the post etch residues were adhered.

Abstract: A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor may be untrained (e.g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor as dependent upon a particular store and the dependency does not actually occur. In one implementation, the STLF predictor records at least a portion of the PC of a store which interferes with the load in a first table indexed by the load PC.

Abstract: The method disclosed herein provides a semiconducting substrate, positioning the substrate in a high density plasma process chamber, and forming a layer of silicon-rich silicon dioxide above the substrate using a high density plasma process with an oxygen/silane flowrate ratio that is less than or equal to 0.625. In another embodiment, the method provides a semiconducting substrate having a partially formed integrated circuit device formed thereabove, the integrated circuit device having a plurality of conductive interconnections, e.g., conductive lines or conductive plugs, formed thereon, and positioning the substrate in a high density plasma process chamber. The method further includes forming a first layer of silicon dioxide between the plurality of conductive interconnections using a high density plasma process with an oxygen/silane flowrate ratio less than 1.0, and forming a layer of insulating material above the first layer between the conductive interconnections.

Abstract: A novel method is provided for initializing a data processing system having registers programmable with configuration data read from a non-volatile memory at power-up. The method includes segmenting the non-volatile memory into a first portion for storing first data, and a second portion for storing second data having lower priority than the first data. The first portion is smaller than the second portion. The first data are read from the first portion to program a first group of registers. Thereafter, the second data are read from the second portion to program a second group of registers. As a result, a host is enabled to access the first group of registers, while the second data are being read from the second memory portion.

Abstract: Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein. The method may comprise employing an anti reflective coating prior to applying a photo resist coating in a semiconductor manufacturing process. Also disclosed are methodologies for exhausting resist residue during development via a rinsing fluid.

Abstract: The present invention relates to systems and methods to regulate spacer deposition. The present invention employs a spacer deposition controller to control a spacer deposition component that deposits a spacer on a portion of a wafer. During and/or after spacer deposition, light can be directed at the spacer, wherein light reflected from the spacer is measured to determine parameters associated with the spacer deposition process. A processor operatively coupled to a measurement system and the spacer deposition controller utilizes the parameters to determine if the spacer process is proceeding in a suitable manner via comparing the measured parameters with stored acceptable parameters. If it is determined that the spacer deposition process is not proceeding as desired, then the measured parameters can be employed by the spacer deposition controller to adjust the spacer deposition process on the portion of the wafer and on subsequent portions of wafers.

Abstract: A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further includes etching the mask and carbon layer to form at least one structure, where the structure has a first width, reducing the width of the carbon layer in the at least one structure to a second width, depositing an oxide layer to surround the at least one structure, removing a portion of the oxide layer and the mask, removing the carbon layer to form an opening in a remaining portion of the oxide layer for each of the at least one structure, filling the at least one opening with conductive material, and removing the remaining portion of the oxide layer and a portion of the conductive layer to form the fin.

Abstract: The present invention relates to systems and methods for increasing the hydrophobicity of patterned resists. In one embodiment, the present invention relates to a method of processing an ultra-thin resist, involving depositing the ultra-thin photoresist over a semiconductor substrate; irradiating the ultra-thin resist with electromagnetic radiation; developing the ultra-thin resist with a developer to form a patterned resist, the patterned resist having a surface with a first hydrophobicity; contacting the patterned resist with a transition solvent to provide the surface of the patterned resist with a second hydrophobicity, wherein the second hydrophobicity is greater than the first hydrophobicity and contact of the patterned resist with the transition is conducted between developing the ultra-thin resist and rinsing patterned resist; and rinsing the patterned resist having the second hydrophobicity with an aqueous solution.

Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The highly absorbing layer of silicon rich nitride has an extinction coefficient (k)>0.5. As reflected light passes through the layer of silicon rich nitride, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the silicon rich nitride in accordance with the pattern formed on the photoresist.

Abstract: A method for presenting performance data from a process flow includes providing a tool link associated with a first subset of the performance data for at least one tool in the process flow; providing a recipe link associated with a second subset of the performance data for at least one recipe in the process flow; displaying the first subset of the performance data in response to the tool link being selected; and displaying the second subset of the performance data in response to the recipe link being selected.