Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The highly absorbing layer of silicon rich nitride has an extinction coefficient (k)>0.5. As reflected light passes through the layer of silicon rich nitride, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the silicon rich nitride in accordance with the pattern formed on the photoresist.

Abstract: A method for presenting performance data from a process flow includes providing a tool link associated with a first subset of the performance data for at least one tool in the process flow; providing a recipe link associated with a second subset of the performance data for at least one recipe in the process flow; displaying the first subset of the performance data in response to the tool link being selected; and displaying the second subset of the performance data in response to the recipe link being selected.

Abstract: The present invention provides a process for saliciding the word lines in a virtual ground array flash memory device without saliciding the substrate between word lines. According to the invention, in a process for manufacturing virtual ground array flash memory devices, a salicide protect layer covers the substrate between word lines in the core region while the tops of the word lines are exposed. The salicide protect layer can be brought into the desired configuration by one or more of masking the substrate between word lines during an etching process, removing salicide protection material in the core by polishing, and forming a comparatively thick layer of salicide protection material in the core whereby the tendency of the salicide protect layer to follow the contour of the underlying structures is reduced. With the substrate between word lines protected by the salicide protect layer, the word lines are salicided.

Abstract: An attenuated phase shift mask utilizes a multilayer which has been locally modified. Heat treatment or e-beam treatment can locally modify the multilayer to provide different reflective characteristics. The attenuated phase shift mask can be utilized in EUV applications.

Abstract: A method of fabricating a semiconductor device having copper (Cu) interconnect lines, formed in vias, whose surfaces are selectively doped with calcium (Ca) ions for preventing electromigration and a device thereby formed. The present invention method reduces electromigration in Cu interconnect lines by restricting Cu diffusion pathways along the interconnect surface. This diffusion restriction is achieved by selectively doping the Cu interconnect surfaces with Ca ions from a chemical solution.

Abstract: A double gate MOSFET. The MOSFET includes a bottom gate electrode and a bottom gate dielectric disposed over the bottom gate electrode. A semiconductor body region is disposed over the bottom gate dielectric and the bottom gate electrode, and disposed between a source and a drain. A top gate electrode is disposed over the body. A top gate dielectric separates the top gate electrode and the body, the top gate electrode and the bottom gate electrode defining a channel within the body and interposed between the source and the drain. At least one of the bottom gate dielectric or the top gate dielectric is formed from a high-K material. A method of forming a double gate MOSFET is also disclosed where a semiconductor film used to form a body is recrystallized using a semiconductor substrate as a seed crystal.

Abstract: A method and system for synchronizing a laser marking device with a lead scanner is disclosed. The laser marking device includes an unloader coupled to the lead scanner and is for marking each of a plurality of semiconductor packages including a plurality of leads. The lead scanner performs a test on the plurality of leads for the plurality of semiconductor packages. The unloader is for containing a portion of the plurality of semiconductor packages that passed the test. The method and system include providing an input receiving circuit, a reset circuit and an output relay. The input receiving circuit is coupled with the unloader and is for receiving an indication of a particular number of the plurality of semiconductor packages received by the unloader.

Abstract: The present invention generally relates to a method of determining a source/drain junction overlap and a channel length of a small device, such as a MOS transistor. A large reference device having a known channel length is provided, and a source, drain, and substrate on which the device has been formed are grounded. A predetermined gate voltage is applied to a gate of the large device, and a gate to channel current of the reference device is measured. A source, drain, and substrate on which the small device has been formed are grounded, and the predetermined voltage is applied to a gate of the small device, and a gate to channel current of the small device is measured. The substrate and one of the source or the drain of the small device is floated, and a predetermined drain voltage is applied to source or the drain which is not floating. A gate to drain current for the small device is measured, and a source/drain junction overlap length is calculated.

Abstract: The present invention provides for a method and an apparatus for automated generation of test semiconductor wafers. At least one process run of semiconductor devices is performed. A determination is made whether an excursion of the process exists. An automated test wafer generation process is performed in response to the determination that an excursion of the process exists. A control parameter modification sequence is implemented in response to an examination of the test wafers.

Abstract: An apparatus and method for controlling temperature during pre-delivery testing of microprocessors and integrated circuits wherein a testing package, including a thermally conductive lid overlying and in thermal contact with the microprocessor or integrated circuit, is covered by a block of thermally conductive material of predetermined thickness T, where T is a function of a desired temperature profile and, optionally, the current drawn by the microprocessor undergoing testing.

Abstract: A method and an apparatus for combining integrated and offline metrology data for process control. A process operation on a first semiconductor wafer within a first lot of semiconductor wafers is performed. Integrated metrology data from the first semiconductor wafer is acquired, the integrated metrology data comprising inline metrology data. A dynamic time process control based upon the integrated metrology data is performed, the dynamic time process control comprising a wafer-to-wafer feedback loop. A second semiconductor wafer within the first lot is processed based upon the dynamic time process. Offline metrology data from at least one of the first semiconductor wafer and the second semiconductor wafer from the lot is acquired. A constant time process control based upon the offline metrology data and the integrated metrology data is performed, the constant time comprising performing a lot-to-lot feedback process.

Abstract: Semiconductor devices comprising interconnect with improved adhesion of barrier layers to dielectric layers are formed by laser thermal annealing exposed surfaces of a dielectric layer in an atmosphere of NH3 and N2, and subsequently depositing Ta to form a composite barrier layer. Embodiments include forming a dual damascene opening in an interlayer dielectric comprising F-containing silicon oxide, such as F-containing silicon oxide derived from F-TEOS, laser thermal annealing the exposed silicon oxide surface in NH3 and N2, depositing Ta and then filling the opening with Cu. Laser thermal annealing in NH3 and N2 depletes the exposed silicon oxide surface of F while forming an N2-rich surface region. Deposited Ta reacts with the N2 in the N2-rich surface region to form a composite barrier layer comprising a graded layer of tantalum nitride and a layer of &agr;-Ta thereon.

Abstract: According to one embodiment of the present invention, a method for determining the location of contaminants on a semiconductor wafer comprises obtaining a first particle count of the wafer, scrubbing the wafer, obtaining a second particle count of the wafer after scrubbing the wafer, and determining the location of the particles based on the first and second particle counts. According to another embodiment of the present invention, a method for determining the source of particle contaminants in a semiconductor processing tool comprises the steps of obtaining a first particle count of a wafer with at least one film deposited thereon, scrubbing the wafer, obtaining a second particle count of the wafer after scrubbing the wafer, and localizing areas of the processing tool where the particle contamination originates from.

Abstract: A semiconductor device and a method of fabricating the semiconductor device having a composite dielectric layer including steps of providing a semiconductor substrate; depositing on the semiconductor substrate alternating sub-layers of a first dielectric material and a second dielectric material to form a layered dielectric structure having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, in which one of the first dielectric material and the second dielectric material is a high-K dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material comprising aluminum oxide; and annealing the layered dielectric structure at an elevated temperature to form a composite dielectric layer.

Abstract: A memory array includes a plurality of sets of transistors, each set including a pair of transistors in series. Each such pair of transistors is connected between a pair of adjacent bit lines. Each of the pair of transistors in each set is associated with a different one of an adjacent pair of word lines. The array is configured by providing substantially strait elongated source/drain regions in side-by-side, parallel relation. Each bit line has a zigzag configuration and connects to a pair of adjacent source/drain regions in alternating manner along the bit line length.

Abstract: A method for repairing over-erasure of floating gate memory devices. Specifically, one embodiment of the present invention discloses a method for performing a program disturb operation on an array of memory cells for repairing over-erasure of fast bits. The program disturb operation is applied simultaneously to the entire array making it compatible with channel erase schemes. The fast bits are programmed back to a normal state above 0 Volts by applying a substrate voltage to a substrate common to the array of memory cells. A gate voltage is applied to a plurality of word lines coupled to control gates of said array of memory cells. A program pulse time for applying voltages ranges from approximately 10 microseconds to 1 second. A voltage differential between a control gate and the substrate in a memory cell is in the range of approximately 9 Volts to about 20 Volts.

Abstract: A system for regulating temperature of a post exposure baking process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being baked and hardened on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the baking and hardening of the respective portions of the wafer. The measuring system provides baking and hardening related data to a processor that determines the baking and hardening of the respective portions of the wafer. The system also includes a plurality of temperature controlling devices, each such device corresponds to a respective portion of the wafer and provides for the heating and/or cooling thereof.

Abstract: A method of memory device fabrication. In one embodiment, the method of memory device (400) fabrication comprises implanting an element (200) in a substrate (440). The element (200) causes an inherent elongational realignment of atoms in silicon (101,102) when silicon (100) is formed (471) upon the substrate (440) with the element (200) implanted therein. A layer of silicon (100) is formed (471) on the substrate having the element (200) implanted therein (470), wherein alignment of atoms (101) of the silicon elongates (102) to an atomical alignment equivalent (101g) to said element (200). The layer of silicon (471) and the substrate (470) are crystallized subsequent to the elongational realignment of atoms of the layer of silicon (101g), wherein a crystallized layer of elongated silicon (101g) decreases electron scattering thus realizing increase core gain in the memory device (400).

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier dielectric material. The dielectric layer around the opening is changed into the barrier dielectric material and the conductor core material is deposited to fill the opening. The conductor core is processed to form a channel for the integrated circuit.

Abstract: A voltage-dependent impedance selector compensates for non-linearities that arise when the operating voltage of an electronic circuit changes. The voltage-dependent impedance selector includes a selection stage that selects a impedance based on the operating voltage of the electronic circuit. The selected impedance is connected to an output stage having a resistive value so that the selected impedance and the output stage form a voltage divider. The voltage-dependent impedance selector may, in some embodiments, be used in reference voltage generation or in impedance matching.