Abstract: The detection of a processing deviation in a cluster tool of a wafer processing system is achieved by assigning individual wafers a set of positional coordinates each time the wafer moves within the cluster tool. In an example embodiment, a wafer is placed into a first chamber of the cluster tool and it is rotated to a certain angle of rotation. Each time the wafer moves within the cluster tool the wafer is given a different angle of rotation; both the rotation angle and the wafer location are then recorded as a set of positional coordinates. The wafer exits the cluster tool and is examined for structural or surface defects that indicate that there was a variation in the processing parameters. A wafer movement map is developed from the positional coordinates and the map is then used as an analysis tool to identify the processing location that caused defect to occur. An important advantage is the increased control and traceability that the tracking method brings to single wafer handling and processing.
Type:
Grant
Filed:
March 8, 2000
Date of Patent:
December 9, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Michael R. Conboy, Sam H. Allen, Jr., Russel Shirley, Elfido Coss, Jr.
Abstract: A method of developing a photoresist layer on a semiconductor wafer in a developing chamber includes applying a developer to the photoresist layer, applying an alcohol rinse to the photoresist layer, and drying the wafer.
Abstract: A network transceiver is configured to receive a complex modulated carrier signal from another network transceiver via a network medium. The complex modulated carrier signal may be payload encoded utilizing one of a plurality of payload encoding specifications based on network distortion characteristics. The transceiver includes an A/D converter and a mixer circuit for generating a baseband I-signal and a baseband Q-signal and a slicer which scales the baseband signals to enable complex decoding constellation coordinates to be integer values and mapping calculations to be performed with integer values.
Abstract: A simultaneous operation flash memory capable of providing double protection to An OTP sector. The preferred simultaneous operation flash memory comprises an OTP write-protect CAM, which is in a programmed state if the OTP sector is write-protected. In addition, the preferred simultaneous flash memory further includes an OTP sector lock CAM that is electrically connected with the OTP write-protect CAM. The OTP sector lock CAM is used to lock the OTP write-protect CAM in the programmed state, which, in turn, will designate the OTP sector as read only.
Abstract: A process for fabrication of a floating gate flash memory device, and the device made thereby, including providing a semiconductor substrate; forming a pad dielectric layer overlying the substrate; forming a hard mask layer overlying the pad dielectric layer; forming an initial trench through the hard mask layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer; reducing the initial lateral extent Li of the initial trench to define a reduced trench having a reduced lateral extent Lrx, wherein x is at least one; and filling the reduced trench with a floating gate material.
Type:
Grant
Filed:
September 16, 2002
Date of Patent:
December 9, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Nian Yang, Zhigang Wang, Hyeon-seag Kim
Abstract: The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper silicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.
Type:
Grant
Filed:
November 12, 2002
Date of Patent:
December 9, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Minh Van Ngo, Shekhar Pramanick, Takeshi Nogami
Abstract: The dimensional accuracy of trench formation and, hence, metal line width, in damascene processing is improved by employing a silicon carbide middle etch stop layer/ARC. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide middle etch stop layer/ARC having an extinction coefficient (k) of about −0.10 to about −0.60.
Type:
Grant
Filed:
February 7, 2001
Date of Patent:
December 2, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Ramkumar Subramanian, Dawn M. Hopper, Fei Wang, Lynne A. Okada
Abstract: A method and an apparatus for detecting a necking error during semiconductor manufacturing. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. Data from a reference library comprising optical data relating to a poly-silicon formation on a semiconductor wafer is accessed. The metrology data is compared to data from the reference library. A fault-detection analysis is performed in response to the comparison of the metrology data and the reference library data.
Abstract: A system for capturing the data necessary for synthesizing an instruction stream for a microprocessor. An embodiment uses a microprocessor that is adapted to write its branch trace data to the main memory. This branch trace data includes whether the microprocessor took each conditional jump encountered during the execution of a program as well as the target location of each indirect jump. The preferred embodiment further includes a logic analyzer coupled to the primary expansion bus of the target computer system. The logic analyzer captures input/output reads and writes as well as DMA transactions to the main memory. Finally, a synthesis control card controls starting a data capture as well as facilitating the transfer of information from buffers in the main memory to the control computer system.
Abstract: A method of manufacturing a semiconductor device includes thermal annealing source/drain regions with a laser, measuring a depth of the source/drain regions, and adjusting a parameter of the laser used in the thermal annealing process. After the laser is adjusted, the source/drain regions are laser thermal annealed again until a desired depth of the source/drain regions is obtained. An apparatus for processing a semiconductor device includes a chamber, a laser, a measuring device, and a controller. The semiconductor device is positioned within the chamber for processing. The laser is used to laser thermal anneal the semiconductor device within the chamber. The measuring device measures a depth of source/drain regions in the semiconductor device when the semiconductor device is within the chamber, and the controller receives measurement information from the measuring device and adjusts parameters of the laser.
Type:
Grant
Filed:
December 13, 2001
Date of Patent:
December 2, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Eric N. Paton, Robert B. Ogle, Bin Yu, Cyrus E. Tabery, Qi Xiang
Abstract: A semiconductor device and method of fabrication are disclosed. The semiconductor device includes a liner composed of a high-K material. The liner has a portion separating a sidewall spacer from a gate and a portion separating the sidewall spacer from a layer of semiconductor material. The liner functions as an etch stop during formation of the sidewall spacer. The liner is removable by an etch process that has substantially no reaction with an isolation region formed in the layer of semiconductor material.
Type:
Grant
Filed:
June 6, 2002
Date of Patent:
December 2, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Qi Xiang, Olov Karlsson, HaiHong Wang, Bin Yu
Abstract: A method of performing a two stage anneal in the formation of an alloy interconnect can include forming a via aperture in a dielectric layer where the via aperture provides an area for formation of a via, providing a seed layer along lateral side walls of the via aperture, rapid thermal annealing the seed layer to facilitate copper grain growth in the via, and slowly annealing the seed layer to facilitate desired distribution of alloy doping. The use of two anneals-one fast (e.g., 60 seconds) at lower temperatures (e.g., 150° C. to 250° C.) and one slow (e.g., minutes to several hours) at higher temperatures (e.g., 200° C. to 450° C.)—helps to control grain growth and alloy doping distribution.
Abstract: A metal gate structure and method of forming the same introduces metal impurities into a first metal layer, made of TiN, for example. The impurities create a surface region of greater etch selectivity that prevents overetching of the TiN during the etching of an overlying tungsten gate during the formation of the metal gate structure. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum as the metal impurities provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.
Type:
Grant
Filed:
August 27, 2002
Date of Patent:
December 2, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Paul R. Besser, Srikanteswara Dakshina-Murthy
Abstract: Raised electrical contacts, such as Pb-alloy solder bumps or balls utilized in semiconductor IC flip-chip devices, are selectively and readily removed from underlying contact pads by means of a chemical etching process, thereby facilitating metallurgical and/or microstructural inspection and/or analysis of the contact pads for failure analysis, void formation, electromigration, diffusion, loss of adhesion, etc., by a variety of optical and microscopic techniques.
Abstract: An apparatus, system, and method are provided for testing an integrated circuit with a probe card having optical fibers. The optical fibers of the probe card are fixed in alignment with test structures in the integrated circuit, and each optical fiber is coupled to an avalanche photo-diode for measuring photoemissions from the test structures. The photoemissions can be analyzed to verify correct circuit behavior. The optical fibers can be alternatives or complements to electrically conductive probes of the probe card.
Type:
Grant
Filed:
September 30, 1999
Date of Patent:
December 2, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Rama R. Goruganthu, Antonio Torres Garcia, Michael R. Bruce
Abstract: A metal interconnect structure and method for making the same provides an alloying elements layer that lines a via in a dielectric layer. The alloying element layer is therefore inserted at a critical electromigration failure site, i.e., at the fast diffusion site below the via in the underlying metal. Once the copper fill is performed in the via, an annealing step allows the alloying element to go into solid solution with the copper in and around the via. The solid solution of the alloying element and copper at the bottom of the via in the copper line improves the electromigration reliability of the structure.
Abstract: A strained silicon MOSFET utilizes a strained silicon layer formed on a silicon germanium layer. Strained silicon and silicon germanium are removed at opposing sides of the gate and are replaced by silicon regions. Deep source and drain regions are implanted in the silicon regions, and the depth of the deep source and drain regions does not extend beyond the depth of the silicon regions. By forming the deep source and drain regions in the silicon regions, detrimental effects of the higher dielectric constant and lower band gap of silicon germanium are reduced.
Abstract: A network switch configured for switching data packets across multiple ports uses decision making device to generate frame forwarding information. The decision making device employs a modular architecture that enables data frames to be processed simultaneously and increase data throughput. The decision making device also includes a memory to store frame headers to minimize the signaling between the decision making device and the receive devices.
Type:
Grant
Filed:
May 28, 1999
Date of Patent:
December 2, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Shashank Merchant, Chandan Egbert, John M. Chiang
Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.
Type:
Grant
Filed:
December 12, 2001
Date of Patent:
December 2, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Pin-Chin Connie Wang, Steven C. Avanzino
Abstract: A method of making organic memory cells made of two electrodes with a controllably conductivce media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The organic semiconductor layer is formed using spin-on techniques with the assistance of certain solvents.
Type:
Grant
Filed:
March 10, 2003
Date of Patent:
December 2, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Jane V. Oglesby, Christopher F. Lyons, Ramkumar Subramanian, Angela T. Hui, Minh Van Ngo, Suzette K. Pangrle