Abstract: A method of making organic memory cells made of two electrodes with a controllably conductivce media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The organic semiconductor layer is formed using spin-on techniques with the assistance of certain solvents.

Abstract: In a semiconductor device including one or more semiconductor containing lines, such as gate electrodes of transistor elements, and/or active areas, sidewall spacer elements of the one or more semiconductor containing lines include a conductive layer that also covers a surface portion of the lines and extends to another semiconductor containing line or an active region to serve as a local interconnect. The sidewall spacer process sequence is modified to obtain the local interconnects along with the sidewall spacers without unduly contributing to process complexity. The conductive layers in the sidewall spacer elements, which may preferably comprise a metal, significantly improve the overall conductivity of these lines. Thus, the present invention offers increased design flexibility and the potential of increasing feature density.

Abstract: A manufacturing method, and an integrated circuit resulting therefrom, has a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.

Abstract: A method is provided, the method comprising programming a silicide fuse by passing a current through the silicide fuse while substantially simultaneously irradiating the silicide fuse with a laser.

Abstract: An SOI device structure is provided which facilitates mitigation of charge build up caused by floating body effects. A ground contact is formed from a top insulating layer to a bottom silicon layer. The ground contact extends through the insulating layer, a stop layer, an isolation region and an oxide layer to the bottom silicon layer. The ground contact is fabricated along with the formation of local interconnects.

Abstract: Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within the die from the back side without breaching the thin insulator layer of the SOI structure. According to an example embodiment, a portion of substrate is removed from the hack side of a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side. Electrical connection is made to a portion of the circuitry within the die via a capacitive coupling arrangement. The electrical connection is used to obtain an electrical measurement from the die that is used for analysis.

Abstract: A method for operating a flash memory includes, in response to a received operation command, initiating an embedded operation of the flash memory and subsequently, during execution of the embedded operation, in response to a received read command, initiating a burst read operation of the flash memory.

Abstract: One aspect of the present invention relates to a system and method for controlling thermal expansion on an EUV mask during EUV photolithography. The system includes an EUV photolithography system for irradiating one or more layers of a wafer through one or more gratings of a patterned EUV mask, whereby heat accumulates on at least a portion of the patterned EUV mask during the irradiation of the one or more layers of the wafer; an EUV mask inspection system for monitoring the one or more gratings on the mask to detect expansion therein, the inspection system producing data relating to the mask; and a temperature control system operatively coupled to the inspection system for making adjustments to the EUV photolithography system in order to compensate for the detected expansion on the mask. The method involves employing feedback and feed forward control to optimize the current and future EUV photolithography processes.

Abstract: A method of manufacturing an integrated circuit includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer and a gate dielectric layer over the semiconductor substrate. Bitlines are implanted closely in the semiconductor substrate and annealed using a rapid thermal anneal. Wordlines and gates are formed and source/drain junctions are implanted in the semiconductor substrate. An interlayer dielectric layer is deposited and the integrated circuit completed.

Abstract: A process for forming sub-lithographic features in an integrated circuit is disclosed herein. A process for enhancing the etch trimmability and the etch stability of features patterned on a photoresist layer is also disclosed herein. The process includes curing a photoresist layer after patterning and development but before an etch process is performed thereon. By controlling the formation of the cured portions of the features patterned on the photoresist layer, the features can be trimmed to sub-lithographic critical dimensions without pattern deformation or occurrence of other failure mechanisms.

Abstract: In a method of reading a memory cell of a memory cell array, electrical potentials are applied to a conductive structure connected to the drain, a conductive structure connected to the source, and the gate of the transistor of a cell to be read. Electrical potential are also applied to a conductive structure connected to the drain, a conductive structure connected to the source, and the gate of the transistor of a reference cell, providing current through the reference cell. The level of resistance to current through the reference cell is chosen by selecting the level of resistance in the conductive structure connected to the source of the transistor of the reference cell.

Abstract: A bus protocol is checked automatically during design or manufacture by connecting a bus protocol monitor to the bus and monitoring signals applied to the bus. The response to those signals is then compared with a predetermined desired response. A signal is generated to alert the protocol designer or manufacturing controller if there is an improper response that indicates that the protocol is in error. The invention is particularly useful as applied to check an LPC bus protocol.

Abstract: An apparatus and method is disclosed for providing a smooth transition between a first clock signal at a first frequency and a second clock signal at a lower second frequency. A pulse is generated that indicates whether the logic levels of the first and the second clock signals are similar or are different. The rising/falling edges of the pulse are synchronized with the rising/falling edges of the first clock signal. When a change in a logic level of a command signal for switching between the clock signals is detected, a first time period is identified in which the logic levels of the first and the second clock signals are different. The transition between the first clock signal and the second clock signal is allowed immediately after the first time period has ended.

Abstract: One aspect of the present invention relates to a method of making a flash memory cell, involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; forming a MDD mask over the substrate, the MDD mask covering the source lines and having openings corresponding to drain lines; and implanting a medium dosage drain implant of a second type to form a drain region in the substrate adjacent the flash memory cell.

Abstract: A memory array includes a plurality of sets of transistors, each set including a pair of transistors in series. Each such pair of transistors is connected between a pair of adjacent bitlines. Each of the pair of transistors in each set is associated with a different one of an adjacent pair of word lines. The array is configured by providing elongated source/drain regions of zigzag configuration in side-by-side relation. Each bit line connects to a pair of adjacent source/drain regions in alternating manner along the bitline length.

Abstract: A memory controller generates speculative and non-speculative memory access requests. Several approaches are used to prevent speculative memory access requests from interfering with non-speculative memory access requests. When a request queue is full and contains at least one speculative request, that request is replaced in the memory access request queue with a non-speculative request. A counter associated with a speculative memory access request counts memory access requests. When a predetermined count value is reach, the speculative memory access request is assumed to be stale and retired from the request queue, thereby reducing possible interference by speculative accesses with non-speculative accesses and/or avoiding wasted bandwidth utilization by stale speculative access requests.

Abstract: A BARC comprising materials having a lower pinhole density than that of silicon oxynitride and materials having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon is employed to reduce deformation of a pattern to be formed in a patternable layer. The patternable layer is formed over a substrate. A multi-layered anti-reflective coating is formed over the patternable layer. A photoresist pattern is formed on the coating. The coating may comprise an amorphous carbon layer formed over the patternable layer and a SiC layer having a lower pinhole density than the pinhole density of SiON formed over the amorphous carbon layer. The coating may also be formed over a polysilicon layer and comprise a thermal expansion buffer layer having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon.

Abstract: A method of manufacturing for a MirrorBit® Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines in the semiconductor substrate. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited thereon. An anti-reflective coating (ARC) material is deposited on the hard mask material and a photoresist material is deposited on the ARC followed by processing the photoresist material and the ARC material to form a photomask of a patterned photoresist and a patterned ARC. The hard mask material is processed using the photomask to form a hard mask. The patterned photoresist is removed and then the patterned ARC without damaging the hard mask or the wordline material. The wordline material is processed using the hard mask to form a wordline and the hard mask is removed without damaging the wordline or the charge-trapping material.

Abstract: An exemplary embodiment relates to a method of shallow trench isolation (STI) formation using amorphous carbon as a sacrificial polish stop layer. The method can include polishing a silicon dioxide layer located above a wafer, polishing portions of the silicon dioxide layer located in a field area and portions of an amorphous carbon layer located in an active area. Portions of the amorphous carbon layer are polished down to a hard polish stop layer. The method can also include ashing away residual amorphous carbon from the amorphous carbon layer.

Abstract: A metal interconnect structure and method for making the same provides an alloying elements layer that lines a via in a dielectric layer. The alloying element layer is therefore inserted at a critical electromigration failure site, i.e., at the fast diffusion site below the via in the underlying metal. Once the copper fill is performed in the via, an annealing step allows the alloying element to go into solid solution with the copper in and around the via. The solid solution of the alloying element and copper at the bottom of the via in the copper line improves the electromigration reliability of the structure.