Abstract: The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in conjunction with SOI type device architecture.

Abstract: A method and apparatus for controlling output impedance of an input/output (I/O) circuit. In one embodiment, an I/O circuit includes a first plurality of resistive elements connected in parallel and a second plurality of resistive elements connected in parallel. Each of the resistive elements includes a control terminal. The control terminal may be used to activate or deactivate the resistive element. The control terminal for each resistive element may be controlled by a control circuit, which may be configured to activate one or more of the resistive elements. Each of the resistive elements of the first plurality may be of substantially different resistances, as may be true with the second plurality of resistive elements. Due to the substantially different resistances of each of the first and second pluralities of resistive elements, the resistive step sizes for the I/O circuit remain substantially equal as additional resistive elements are activated.

Abstract: An apparatus and method for detecting an endpoint for an etching process utilize a reaction chamber with an ion source and detector placed within the reaction chamber. The ion source directs a primary beam of ions towards a wafer so that the ion beam impacts the top layer of the wafer. A detector detects primary ions reflected from the wafer and secondary ions scattered from the wafer. A value is determined that corresponds to the amount of reflected and scattered ions. A change in the value indicates that the ion beam is impacting a layer beneath the top layer of the wafer, and signifies the reaching of the etch process endpoint.

Abstract: A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. A barrier layer is deposited on the PVD amorphous silicon layer. The metal is then formed on the barrier layer. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer. The barrier layer prevents interaction between the PVD amorphous silicon layer and the metal, thereby allowing higher temperature subsequent processing while preserving the work function of the gate.

Abstract: A Fluorine doped Silicon Oxide (SiO2)/Tantalum interface and method for manufacturing the same are provided that ensure the structural integrity of integrated circuits that include a Fluorine doped Silicon Oxide structure and a corresponding Tantalum barrier layer. The Fluorine doped Silicon Oxide (SiO2)/Tantalum interface comprises an amount of Silicon Nitride (SiN) in a surface region of a Fluorine doped Silicon Oxide structure. The concentration of Fluorine in the surface region is depleted with respect to a concentration of Fluorine in the remaining portion(s) of the Fluorine doped Silicon Oxide structure. The Fluorine doped Silicon Oxide (SiO2)/Tantalum interface also includes an amount of Tantalum Nitride (TaN) in the surface region. Finally, a Tantalum barrier layer is deposited over the surface region.

Abstract: The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.

Abstract: A method for providing a modified threshold voltage distribution for a dynamic reference array in a flash memory cell array. The dynamic reference array and an associated core memory cell array are programmed using two different programming processes to produce different Vt distributions for the dynamic reference array and the core memory cell array. The dynamic reference array is programmed using a finer program pulse to achieve a smaller distribution width, thus enhancing the read margin for the memory cell array. The finer pulse may be of shorter duration or of smaller amplitude. The finer programming process may be applied to one or more threshold voltage distributions (states) in the memory cell array.

Abstract: The present invention is generally directed to various methods of detecting degradation in photolithography processes based upon scatterometric measurements of grating structures, and a device comprising such structures. In one embodiment, the method comprises providing a wafer comprised of a plurality of grating structures, each of the grating structures being comprised of a plurality of features, each of the grating structures having a different critical dimension, illuminating at least one of the grating structures, measuring light reflected off of at least one of the grating structures to generate an optical characteristic trace for the grating structure, and determining the presence of residual photoresist material between the features of the grating structure by comparing the generated optical characteristic trace to at least one optical characteristic trace from a library. In some embodiments, the grating structures are arranged in a linear array.

Abstract: A system for regulating heating temperature of a material is provided. The material may be a photoresist, a top or bottom anti-reflective coating, a low K dielectric material, SOG or other spin-on material, for example. The system includes a plurality of lamps and optical fibers, each optical fiber directing radiation to and heating a respective portions of a bakeplate on which the material is to be placed. In one embodiment, the temperature at various locations on the material placed on the bakeplate is determined and the heating rates are controlled in response to those measurements. In another aspect of the invention, the temperature at various portions of the bakeplate is determined and controlled. In this latter aspect, uniform heating of the material is a consequence of uniform bakeplate temperature.

Abstract: The present invention relates to a system and a method for reducing the linewidth of ultra thin resist features. The present invention accomplishes this end by applying a densification process to an ultra thin resist having a thickness of less than about 2500 Å formed over a semiconductor structure. In one aspect of the present invention, the method includes providing a semiconductor substrate having a device film layer formed thereon. An ultra thin resist is then deposited over the device film layer. The ultra thin resist is patterned according to a desired structure or feature using conventional photolithography techniques. Following development, the ultra thin resist is implanted with a dopant. After the implantation is substantially completed, the device film layer is anisotropically etched.

Abstract: A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of suicide shorting through shallow source/drain junctions. Embodiments include doping the semiconducting sidewall spacers so that they serve as a source of impurities for forming source/drain extensions during activation annealing.

Abstract: Silicon on insulator technology and strained silicon technology provide semiconductor devices with high performance capabilities. Shallow trench isolation technology provides smaller devices with increased reliability. Bulk silicon technology provides devices requiring deep ion implant capabilities and/or a high degree of thermal management. A semiconductor device including silicon on insulator regions, strained silicon layer, shallow trench isolation structures, and bulk silicon regions is provided on a single semiconductor substrate.

Abstract: Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphized regions to form first deep halo implants, laser thermal annealing to recrystallize the first deep amorphized regions and activate the deep halo regions, ion implanting to form second shallow amorphized regions within the deep halo regions, ion implanting an impurity into the second shallow amorphous regions to form second shallow halo implants and laser thermal annealing to recrystallize the second shallow amorphous regions and to activate the shallow halo regions. Embodiments further include forming shallow source/drain extensions within the shallow halo implants and laser thermal annealing to activate the shallow source/drain extensions.

Abstract: The present invention provides for a method and an apparatus for using scatterometry to perform feedback and feed-forward control. A processing run of semiconductor devices is performed. Metrology data from the processed semiconductor devices is acquired. Error data is acquired by analyzing the acquired metrology data. A determination is made whether the error data merits modification to the processing of semiconductor devices. A feedback modification of the processing of semiconductor devices is performed in response to the determination that the error data merits modification to the processing of semiconductor devices. A feed-forward modification of the processing of the semiconductor devices is performed in response to the determination that the error data merits modification to the processing of semiconductor devices.

Abstract: A process for fabrication of a semiconductor device including a modified ONO structure, comprising forming the modified ONO structure by providing a semiconductor substrate; forming a first dielectric material layer on the semiconductor substrate; depositing a silicon nitride layer on the first dielectric material layer; and forming a top dielectric material layer, wherein at least one of the bottom dielectric material layer and the top dielectric material layer comprise a mid-K or a high-K dielectric material. The semiconductor device may be, e.g., a SONOS two-bit EEPROM device or a floating gate flash device including the modified ONO structure.

Abstract: An apparatus and a method of depositing a dielectric material film, including steps of initiating a process of depositing a dielectric material film under at least one controllable initial condition in an apparatus comprising a dielectric material deposition chamber and a spectroscopic ellipsometer; and measuring, by the spectroscopic ellipsometer, at least one ellipsometric parameter of the dielectric material film during the process of depositing the film.

Abstract: An asymmetric multi-converter power supply including a first converter and a second converter coupled to provide power to an output node. A control circuit is coupled to the second converter and is configured to selectively enable the second converter depending upon a voltage at the output node. The control circuit may be configured to enable the second converter only in response to determining that the voltage at the output node is not within a predetermined range. Alternatively, the first converter is configured to provide power through a first series inductor and the second converter is configured to provide power to the output node through a second series inductor. The second series inductor having a smaller inductance than the first series inductor. Additionally, the second converter may be characterized by a transient response time that is faster than a transient response time of the first converter.

Abstract: A semiconductor structure and a process for its manufacture. A metal gate electrode is formed on a semiconductor substrate, the gate electrode being between nitride spacers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions.

Abstract: A heat sink subassembly may include a retainer comprising several attachment points, a heat sink coupled to the retainer, and a force-generating device. The heat sink includes several fins, one of which is shorter than the other fins. The force-generating device is coupled to at least one of the attachment points and to the first fin. The force-generating device is configured to exert a force that keeps the heat sink securely coupled to the retainer when the force-generating device is coupled to the attachment points.

Abstract: The present invention is generally directed to various methods for determining, tracking and/or controlling processing based upon wafer characteristics. In one embodiment, the method is directed to selecting a plurality of wafers from the group of wafers based upon the semiconductor device to be manufactured on the wafer and at least one characteristic of the wafers. In another embodiment, the method comprises identifying a source of wafers wherein the device metrology data lies outside of the preselected range based upon the wafer identification mark and the device metrology data. As yet another example, the method comprises determining at least one parameter of a process operation to be performed on a wafer in a processing tool based upon the determined wafer characteristics.