Abstract: A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters.

Abstract: An I/O device configured for accessing a system memory via a peripheral bus minimizes I/O read accesses required by a CPU, by copying an interrupt status value from its interrupt register to a prescribed location in the system memory. Once the interrupt status value is copied into system memory, the I/O device generates an interrupt to notify the CPU of an interrupt condition requiring servicing. Hence, the interrupt status value stored in system memory enables the CPU to service the interrupt based on reading the interrupt status value from system memory, eliminating the necessity of performing an I/O read operation of the interrupt register within the I/O device via a peripheral bus.

Abstract: An address relocation cache includes a plurality of entries. Each of the plurality of entries is configured to store at least a portion of an input address, at least a portion of an output address to which the input address translates, and a destination identifier corresponding to the output address. An input address may be translated to the output address and the corresponding destination identifier may be obtained concurrently for input addresses which hit in the address relocation cache. If an input address misses in the address relocation cache, a translation corresponding to the address may be located for storing into the address relocation cache. The output address indicated by the translation may be passed through the address map to obtain the destination identifier, and the destination identifier may be stored in the address relocation cache along with the output address.

Abstract: A method of fabricating a semiconductor device, having an interim reduced-oxygen Cu-Zn alloy thin film (30) electroplated on a blanket Cu surface (20) disposed in a via (6) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin film (30); filling the via (6) with further Cu (26); annealing and planarizing the interconnect structure (35); and a semiconductor device thereby formed.

Abstract: A process tool comprised of an adjustable wafer stage and various methods and systems for performing process operations using same is disclosed herein. In one illustrative embodiment, the process tool is comprised of a process chamber, and an adjustable wafer stage in the process chamber to receive a wafer positioned thereabove, the wafer stage having a surface that is adapted to be raised, lowered or tilted. In further embodiments, the process tool further comprises at least three pneumatic cylinders or at least three rack and pinion combinations, each of which are operatively coupled to the wafer stage by a ball and socket connection.

Abstract: A semiconductor packaging apparatus for preventing cracking and delamination in a packaged semiconductor chip by controlling the die attach fillet height. Specifically, the present invention controls the die attach material height, thereby controlling the die attach fillet height, and thereby reducing shear stress in the die itself. Advantages of the present invention include increasing wire-bond reliability and package reliability without the need for requalification of existing products. By using currently qualified molding compounds and die attach epoxies in conjunction with the present technique for controlling the die attach epoxy height in order to control the die attach fillet height, the overall assembly process may be maintained. Thus, neither thermal performance nor electrical performance is compromised.

Abstract: A method comprising performing an etch process recipe comprised of an endpoint etch process and a timed over-etch process on each of a first plurality of substrates to form at least one opening in each layer of insulating material, determining a duration of the endpoint etch process performed on the first plurality of substrates, determining a duration of the timed over-etch process of the etch process recipe to be performed on a second plurality of substrates based upon the determined duration of the endpoint etch process performed on the first plurality of substrates, and performing the etch process recipe comprised of the endpoint etch process and the timed over-etch process of the determined duration on the second plurality of semiconducting substrates.

Abstract: Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

Abstract: Excessive variation in vertical (i.e., inter-level) capacitance of multi-level metallization semiconductor devices resulting in racing of clock skew circuitry of finished devices, and over-etching of borderless vias leading to inter-level short-circuits, are simultaneously eliminated, or substantially reduced, by selectively providing an etch-resistant masking material at thinner, i.e., recessed, portions of a first, low k gap fill material blanket-deposited over spaced-apart features of a metallization pattern and in the spaces therebetween. The surfaces of thicker, non-recessed portions thereof are etched so as to be substantially co-planar with the feature surfaces and the recessed portions. The etch-resistant mask is then removed, and second, oxide-based and third, low k dielectric layers deposited over the planarized surface.

Abstract: A method for forming a dual damascene conductive line and conductive plug using porous low k dielectric materials in the via and trench layers. The via layer is provided with dense low k dielectric plugs that increase the mechanical strength of the porous low k dielectric layer that forms the via layer. A via fill technique etches some of the dielectric plugs in the via layer and fills them with conductive material. The via fill technique reduces the damage done to the via holes in the via layer caused by photoresist removal processes.

Abstract: An apparatus includes a buffer configured to store information corresponding to store memory operations and circuitry to detect a load which hits one of the stores represented in the buffer. More particularly, the circuitry may compare the index portion of the load address to the index portions of the store addresses stored in the buffer. If the indexes match and both the load and the store are a hit in the data cache, then the load and store are accessing the same cache line. If one or more bytes within the cache line are updated by the store and read by the load, then the store data is forwarded for the load. In one embodiment, the circuitry speculatively forwards data if the load and store indexes match and the store is a hit in the data cache. Subsequently, when the load is determined to hit/miss in the cache, the forwarding is verified using the load's hit/miss indication.

Abstract: The present invention is directed to several inventive methods for characterizing implant profiles. In one embodiment, the method comprises providing a semiconducting substrate, forming a first plurality of implant regions in the substrate, and illuminating at least one of the first plurality of implant regions with a light source in a scatterometry tool, wherein the scatterometry tool generates a profile trace corresponding to an implant profile of the illuminated implant region. The method further comprises creating at least one profile trace corresponding,to an anticipated profile of the implant region, wherein, in creating the profile trace, values of at least one of an index of refraction (n) and a dielectric constant (k) are varied, and comparing the generated profile trace to at least one created profile trace.

Abstract: Integrated circuit analysis is enhanced via a method and system for detecting defects associated with particular logic states of an integrated circuit. According to an example embodiment of the present invention, a constant current supply is applied to an integrated circuit. The voltage across the constant current supply is detected for each of a plurality of clock cycles of the integrated circuit, each clock cycle being representative of a logic state of the integrated circuit. The voltage detected at each clock cycle is compared, and the comparison is used to analyze the integrated circuit for a defect.

Abstract: A method of forming ultra-shallow junctions in a semiconductor wafer forms the gate and source/drain junctions having upper surfaces at first metal suicide regions on the gate and source/drain junctions. These first metal silicide regions have a higher resistivity. Amorphous silicon is deposited on the first metal suicide regions by plasma enhanced chemical vapor deposition (PECVD). The PECVD process may be a lower pressure deposition process, performed at multiple stations to form the amorphous silicon layer in multiple layers. This creates a more uniform amorphous silicon layer across the wafer and different patterning densities, thereby improving device performance and characteristics. Annealing is then performed to form second metal silicide regions of a lower resistivity, by diffusion reaction of the first metal silicide regions and the amorphous silicon that was deposited by the PECVD process.

Abstract: A process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mask. The protective layer is etched using the silyated photoresist mask as an etch mask, and then the organic dielectric layer is etched using the silyated photoresist mask as an etch mask. Metal may be deposited in a void etched in the organic dielectric layer to form a wiring, contact or via.

Abstract: Management of move requests from a factory system to an automated handling system (AMHS) is provided. In one embodiment, a method and system is provided which includes receiving a move request from the factory system and selectively passing the move request to the AMHS based on a comparison of the move request with one or more conditions of the AMHS. The move request may be selectively passed to the AMHS by, for example, passing the move request to the AMHS without modification, changing a destination tool identified in the move request and/or delaying the move request, or canceling the move request. By selectively passing the move request based on conditions of the AMHS, move requests can more efficiently be managed and the throughput of the automated material handling system can be increased.

Abstract: A semiconductor device, a semiconductor wafer and a method of forming a semiconductor wafer where a barrier layer is used to inhibit P-type ion-penetration into a dielectric layer made from a high-K material.

Abstract: A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon.

Abstract: A CMOS device (10) having p-channel and n-channel transistors with aluminum implanted gates (20). When making the device (10), aluminum is non-selectively implanted to form a source and drain for the n-channel transistor and to reduce the resistivity of the gates (20). The aluminum diffuses through an upper polysilicon layer (22) of the gate, thereby reducing its resistivity, but does not diffuse through a lower oxide layer (24) of the gate, thereby preventing penetration problems. Thereafter, a compensating implant (e.g., phosphorus or arsenic) is selectively implanted to overcompensate the boron previously implanted in the p-type tub.

Abstract: The present invention is directed to a method of controlling stepper process parameters based upon optical properties of incoming process layers, and a system for accomplishing same. In one embodiment, the method comprises forming a film stack comprised of at least one process layer and a layer of photoresist, illuminating the film stack, and measuring light reflected off the film stack to generate an optical characteristic trace for the film stack. The method further comprises comparing the generated optical characteristic trace to a target optical characteristic trace, and modifying, based upon a deviation between the generated optical characteristic trace and the target optical characteristic trace, at least one parameter of an exposure process to be performed on the film stack.