Abstract: An insulated trench isolation structure is formed by ion implanting impurities proximate to the trench edges for enhancing the oxidation rate and, hence, increasing the thickness of the oxide at the trench edges. Embodiments include ion implanting impurities prior to growing an oxide liner. The resulting thick oxide on the trench edges avoids overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.
Type:
Grant
Filed:
November 5, 1998
Date of Patent:
July 29, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Nick Kepler, Olov Karlsson, Larry Wang, Basab Bandyopadhyay, Effiong Ibok, Christopher F. Lyons
Abstract: A self-aligned transistor including a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region. The channel region has a first side and a second side and a top portion, and a gate oxide surrounds the channel on said first side, second side and top portion. A first, a second and a third silicon gate regions are positioned in a second silicon portion surrounding the first silicon portion about the first side, second side and top portion and the channel region.
Abstract: A system and method are disclosed for providing in-situ monitoring of an oxidized ARC layer disposed over an ARC layer. By monitoring the thickness of the oxidized portion of the ARC layer during semiconductor processing, one or more process control parameters may be adjusted to help achieve a desired oxidized portion thickness.
Type:
Grant
Filed:
June 13, 2001
Date of Patent:
July 22, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Bhanwar Singh, Cristina Cheung, Jay Bhakta, Carmen Morales, Junwei Bao
Abstract: The present invention is directed to a method of polishing wafers on a polishing tool comprised of first, second and third platens. The method comprises providing a wafer having a patterned layer of insulating material, a barrier metal layer, and a metal layer formed above the wafer, performing a first polishing operation on the wafer at the first platen to remove a majority of the metal layer above the barrier metal layer, and performing an endpoint polishing operation on the wafer at the second platen to remove at least some of the metal layer.
Type:
Grant
Filed:
March 26, 2001
Date of Patent:
July 22, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Joyce S. Oey Hewett, Gerd Franz Christian Marxsen, Anthony J. Toprac
Abstract: The present invention relates to a methodology of fabricating a local interconnect. The methodology includes the steps of forming an organic stop layer over a semiconductor structure having at least one conductive region, forming an insulating layer over the organic layer, forming a photoresist layer over the insulating layer, patterning the photoresist layer with at least one opening above the at least one conductive region, etching at least one opening in the insulating layer, concurrently stripping the photoresist layer and an exposed portion of the organic layer and filling the at least one opening with a conductive material to form the local interconnect.
Abstract: A semiconductor device includes a T-shaped gate electrode. The T-shaped electrode may have a metal upper layer and a semiconductor lower layer with a diffusion barrier therebetween. The metal upper layer may be used as a gate mask to control implantation of ions in a semiconductor substrate. Gate metal-semiconductor portions may be electrically coupled to both the metal upper portion and the semiconductor lower portion thereby to reduce electrical resistance in the T-shaped electrode. A method of forming source and drain regions in the semiconductor device includes using the T-shaped gate electrode as an implant mask.
Abstract: An exemplary embodiment relates to a method of pinhole decoration and detection. The method can include providing a material layer above an amorphous carbon layer where the material layer has a pinhole, providing a film over the material layer where the film has a substantially planar surface except above the pinhole, and detecting the pinhole by detecting a non-planar location on the substantially planar surface of the film.
Type:
Grant
Filed:
June 26, 2002
Date of Patent:
July 22, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
David Lin, Scott A. Bell, Philip A. Fisher, Srikanteswara Dakshina-Murthy
Abstract: The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the surface from the dielectric field and from between the lines after CMP by immersing the wafer in a bath containing a chemical agent. Embodiments include removing up to 60 Å of silicon oxide by immersing the wafer in an acidic solution, such as a solution of hydrofluoric acid and water.
Type:
Grant
Filed:
December 7, 1998
Date of Patent:
July 22, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Diana M. Schonauer, Steven C. Avanzino, Kai Yang
Abstract: A method of manufacturing a semiconductor device with a reduced bit-line isolation dimension. After a layer of image sensitive photoresist is patterned and developed with openings having the minimum printable dimension, the layer of photoresist is silylated causing the layer of photoresist to swell, which causes the opening dimension to decrease.
Type:
Grant
Filed:
December 18, 2000
Date of Patent:
July 22, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Allen S. Yu, Chau M. Ho, Paul J. Steffan
Abstract: A low resistance common source line (12) for high performance NOR-type flash memories cells in different bit-lines but on the same word-line is used to reduce the memory core cell size and to improve the circuit density as the device dimensions are scaled down. For advanced flash memory technology where shallow trench isolation (STI) (4) is used, the common source formation (12) is facilitated by a VCI implant (11) performed before STI field oxide fill (5). The process sequence is to first form the trenches (4) for the subsequent STI (4), then apply the VCI mask (10) and perform the VCI high energy ion implant (11) to form the “future” source line (12). Then field oxide fill (5) is deposited into the STI trench (4) to form the desired field isolation structures and the memory circuit is completed using conventional techniques.
Abstract: A storage circuit for an integrated circuit is configured to couple to a first power supply voltage (e.g. a Vdd power supply voltage used by other circuitry within the integrated circuit) in response to a deassertion of a hold signal and configured to couple to a second power supply in response to an assertion of the hold signal. The second power supply voltage may be the hold signal voltage or another power supply voltage separate from the Vdd power supply voltage. The hold signal may be asserted and the Vdd power supply voltage may be removed. Leakage current in circuits powered only by the Vdd power supply voltage may be eliminated, while the storage circuit may retain its stored value. A system including the integrated circuit and a method for managing power in the system.
Abstract: A network switch arrangement and method for providing a common architecture for queuing and dequeuing of data frames as they are transferred from a switch port to an external memory and similarly retrieved from the external memory to the switch port, irrespective of the particular data rate of the port. Logic controlling the actual data path is partitioned from logic responding to port data rate information by providing a “handshaking” communication arrangement between the two logics independent of the data rate. Hence, scalability of the data path over a wide range of data rates may be achieved while maintaining a single, common logic architecture.
Abstract: A method and an apparatus for performing periodic correction of metrology data. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. At least one test wafer is processed. Test wafer metrology data from the processed test wafer is acquired. A test wafer metrology calibration process is performed upon the acquired metrology data using the acquired test wafer metrology data to produce a calibrated metrology data.
Abstract: A package assembly is formed by applying flux to a substrate and inspecting the applied flux to determine whether the amount applied is adequate to form reliable interconnections between a device and the substrate. Embodiments include applying a rosin based flux on a laminate substrate and inspecting the coverage of the applied flux by fluorescent spectroscopy.
Type:
Grant
Filed:
July 28, 2000
Date of Patent:
July 22, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Jonathan D. Halderman, Terri J. Brownfield
Abstract: The integrity of the interface and adhesion between a barrier or capping layer and a Cu or Cu alloy interconnect member is significantly enhanced by delaying and/or slowly ramping up the introduction of silane to deposit a silicon nitride capping layer after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma. Other embodiments include purging the reaction chamber with nitrogen at elevated temperature to remove residual gases prior to introducing the wafer for plasma treatment.
Type:
Grant
Filed:
July 26, 2000
Date of Patent:
July 22, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Minh Van Ngo, Hartmut Ruelke, Lothar Mergili, Joerg Hohage, Lu You, Robert A. Huertas, Richard J. Huang
Abstract: An operating system resource, configured for establishing communications between consumer processes configured for generating respective work notifications and a host channel adapter configured for servicing the work notifications, assigns virtual address space for use by the consumer processes in executing memory accesses, and respective unique mapping values. An address translator includes a translation map for uniquely mapping the virtual address space used by the consumer processes to a prescribed physical address space accessible by the host channel adapter. The address translator, in response to receiving from an identified consumer process the work notification at a virtual address, maps the work notification to a corresponding prescribed physical address based on the corresponding mapping value assigned to the identified consumer process, enabling the host channel adapter to detect the work notification for the consumer process.
Type:
Grant
Filed:
December 12, 2001
Date of Patent:
July 22, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Joseph A. Bailey, Norman Hack, Rodney Schmidt
Abstract: A method of forming an oxide layer on a substrate comprises deposition of a mask layer with an opening for defining the area where the oxide layer is to be formed, and an ion implantation step performed with a tilt angle so as to obtain a varying ion concentration. In a subsequent single oxidation step, an oxide layer is formed having a thickness that varies in conformity with the ion concentration. This method may advantageously be applied to the formation of a gate insulation layer in a field effect transistor.
Type:
Grant
Filed:
March 14, 2001
Date of Patent:
July 15, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Thomas Feudel, Manfred Horstmann, Christian Krüger
Abstract: An apparatus and method are capable of a process to planarize a surface of a conductive layer on a semiconductor wafer. The method includes bringing a temperature of the conductive layer to within a predetermined range below a melting point of the conductive layer and holding the temperature of the conductive layer within the predetermined range to allow the conductive layer to undergo strain via at least one creep mechanism due to a weight of the conductive layer. The conductive layer is then cooled.
Abstract: A method for making an SOI semiconductor device including a silicon substrate includes implanting oxide and Nitrogen into the substrate and then annealing to drive Oxygen and Nitrogen through and below the buried oxide layer. The implanted species interact with the Silicon matrix of the substrate to establish field isolation areas that extend deeper than the buried oxide layer of the SOI device, to ensure adequate component isolation.
Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a nozzle adapted to apply a predetermined volume of developer material on a photoresist material layer along a linear path having a length approximately equal to the diameter of the photoresist material layer. A movement system moves the nozzle to a first position offset from a central region of the photoresist material layer for applying a first predetermined volume of developer material to the photoresist material layer while the developer material is spin coated. The movement system also moves the nozzle to a second position offset from the central region for applying a second predetermined volume of developer material to the photoresist material layer while the developer is spin coated. The first position is located on an opposite side of the central region with respect to the second position.
Type:
Grant
Filed:
March 21, 2001
Date of Patent:
July 15, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Michael K. Templeton, Sanjay K. Yedur