Abstract: One aspect of the present invention relates to an in-line system for monitoring and optimizing an on-going CMP process in order to determine a CMP process endpoint comprising a wafer, wherein the wafer is subjected to the CMP process; a CMP process monitoring system for generating a signature related to wafer dimensions for the wafer subjected to the CMP process; and a signature library to which the generated signature is compared to determine a state of the wafer. Another aspect relates to an in-line method for monitoring and optimizing an on-going CMP process involving providing a wafer, wherein the wafer is subjected to a CMP process; generating a signature associated with the wafer; comparing the generated signature to a signature library to determine a state of the wafer; and using a closed-loop feedback control system for modifying the on-going CMP process according to the determined state of the wafer.

Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a nozzle adapted to apply a predetermined volume of developer material on a photoresist material layer along a linear path having a length approximately equal to the diameter of the photoresist material layer. A movement system moves the nozzle to a first position offset from a central region of the photoresist material layer for applying a first predetermined volume of developer material to the photoresist material layer while the developer material is spin coated. The movement system also moves the nozzle to a second position offset from the central region for applying a second predetermined volume of developer material to the photoresist material layer while the developer is spin coated. The first position is located on an opposite side of the central region with respect to the second position.

Abstract: The present invention provides systems, methods, and standards for calibrating nano-measuring devices. Calibration standards of the invention include carbon nanotubes and methods of the invention involve scanning carbon nanotubes using nano-scale measuring devices. The widths of the carbon nanotube calibration standards are known with a high degree of accuracy. The invention allows calibration of a wide variety of nano-scale measuring devices, taking into account many, and in some cases all, of the systematic errors that may affect a nano-scale measurement. The invention may be used to accurately calibrate line width, line height, and trench width measurements and may be used to precisely characterize both scanning probe microscope tips and electron microscope beams.

Abstract: A pellicle utilizes a thin film attached to a frame. The film is relatively transparent to radiation. The frame is coupled to a periphery of the film and is exclusive of the center portion of the film. The pellicle can be manufactured by growing a relatively transparent film on a silicon substrate and removing the substrate to expose at least a portion of the relatively transparent film.

Abstract: The present invention relates to a system for controlling a thin film formation process using a corona discharge measurement technique. The system includes a thin film formation system operative to form a thin film based on one or more process parameters, a corona discharge measurement system operable to measure one or more properties of the thin film, and a processor operatively coupled to the thin film formation system and the corona discharge measurement system, wherein the processor analyzes the data from the corona discharge measurement system and a set of target data and controls the one or more process parameters via the thin film formation system based on the analysis. The present invention also relates to a method for controlling a thin film formation using a corona discharge technique.

Abstract: In a method for mounting an integrated circuit onto a substrate in a flip-chip configuration, a circuit alignment feature on the processed surface of the integrated circuit and a substrate alignment feature on the mounting surface of the substrate are used to accurately align a set of bonding pads on the processed surface of the integrated circuit with a corresponding set of contact pads on the mounting surface of the substrate. The positions of the circuit and substrate alignment features are determined, and a separation between these alignment features which will result in accurate alignment of the bonding pads to the corresponding contact pads is calculated. The circuit is moved with respect to the substrate in order to achieve this predetermined separation. The method may be carried out using an apparatus which includes a die placement fixture and a substrate placement fixture.

Abstract: There is provided a communication network and method for enhancing server availability to client PCS which includes two Ethernet switches. Each one of the two Ethernet switches is connected to a corresponding one of the primary and secondary network interface cards in the file server PC. The two Ethernet switches are interconnected together through an uplink port. As a result, redundancy has been effectively and efficiently provided against the failure of either one of the two switches in order to enable link fail-over across two network segments.

Abstract: A method for monitoring health of a tool includes receiving at least one tool parameter related to the processing of a workpiece in a tool; receiving a model selection trigger; selecting a tool health model based on the model selection trigger; generating at least one predicted tool parameter based on the selected tool health model; and generating a tool health rating for the tool based on a comparison between the measured tool parameter and the predicted tool parameter. A tool health monitor includes a library of tool health models, a model selector, and a fault detection and classification unit. The model selector is adapted to receive a model selection trigger and select a tool health model based on the model selection trigger.

Abstract: This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a sidewall spacer masking procedure, both for defining the device isolation features and the source and drain regions. The active region is defined after patterning the gate electrode by means of deposition and etch processes instead of overlay alignment technique. Thus, the present invention enables an increase of the integration density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

Abstract: A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56).

Abstract: A reflective mask or reticle configured to reduce reflections from an absorptive layer during lithography at a wavelength shorter than in a deep ultraviolet (DUV) range is disclosed herein. The reflective mask or reticle is configured to generate additional reflections which have a desirable phase difference with respect to the reflections from the absorptive layer. The additional reflections reduce or eliminate the reflections from the absorptive layer by destructive interference.

Abstract: A flash memory microelectronic chip (1000) is formed with at least one integral test structure (100) for electrical measurement of transistor leakage current from the low voltage peripheral transistors. The invention is a very wide finger-type transistor (9, 10) with minimum channel length and a width of approximately 150,000 &mgr;m, equal to the estimated total width of the same type of periphery transistors in the chip circuit. One low voltage NMOS (9) and one low voltage PMOS finger-type transistor (10) allow monitoring of the standby current contribution from these two types of periphery transistors. Regular current or voltage tests can be applied to the test structure, thus providing information on the correlation of standby currents with single transistor off-state leakage currents.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening and a conductor core filling the channel opening. A via stop layer is formed over the channel dielectric layer to have a hydrogen concentration below 15 atomic % and a via dielectric layer is formed over the via stop layer and has a via opening. A second channel dielectric layer over the via dielectric layer has a second channel opening. A second conductor core, filling the second channel opening and the via opening, is connected to the semiconductor device.

Abstract: One aspect of the present invention relates to a method of forming trench isolation regions within a semiconductor substrate, involving the steps of forming trenches in the semiconductor substrate; depositing a semi-conformal dielectric material over the substrate, wherein the semi-conformal dielectric material has valleys positioned over the trenches; forming an inorganic conformal film over the semi-conformal dielectric material; polishing the semiconductor substrate whereby a first portion of the inorganic conformal film is removed thereby exposing a portion of the semi-conformal dielectric material, and a second portion remains over the valleys of the semi-conformal dielectric material; removing the exposed portions of the semi-conformal dielectric material; and planarizing the substrate to provide the semiconductor substrate having trenches with a dielectric material therein.

Abstract: The capacitance between the gate of a transistor and local interconnect is reduced employing SiC as an etch stop layer. Embodiments include depositing a SiC etch stop layer having a thickness of about 500-1000 Å and a dielectric constant of less than about 3.2, thereby providing a composite dielectric constant between the gate and local interconnect of between about 3.7 to about 4.7. The SiC etch stop layer can be deposited by PECVD or HDP techniques.

Abstract: An exemplary method of using developer as a solvent to spread photoresist faster and reduce photoresist consumption can include dispensing a developer solution onto an integrated circuit wafer, spinning the integrated circuit wafer to distribute the developer solution over the integrated circuit wafer, and dispensing a photoresist solution onto the integrated circuit covered with the developer solution.

Abstract: A photoresist mask used in the fabrication of integrated circuits, can include a first portion and a second portion. The first portion has a phase shifting material layer and an opaque layer deposed over a transparent layer. The first portion also has trenches in the transparent layer selectively located to provide an alternating phase shifting characteristic. The second portion has the opaque layer deposed over the phase shifting material layer which is deposed over the transparent layer.

Abstract: A method for controlling wafer uniformity in a polishing tool includes providing a plurality of carrier heads, determining a signature for each of the carrier heads, and installing carrier heads with similar signatures in a polishing tool. A processing line includes a polishing tool and a processing tool. The polishing tool is adapted to polish wafers. The polishing tool includes a plurality of carrier heads, each carrier head having a polishing signature similar to the other carrier heads. The processing tool is adapted to process the polished wafers in accordance with a recipe. At least one parameter in the recipe is based on the polishing signatures of the carrier heads.

Abstract: An array of memory cells includes a plurality of memory cells interconnected via a grid of M wordlines and M bitlines, wherein M=2, 3, 4, 5, . . . wherein each of the M bitlines is buried. The array further includes a plurality of contacts, wherein each of the plurality of contacts is formed every N wordlines, N=1, 2, 3, . . . , wherein each of the plurality of contacts overlies a gate of a different one of the plurality of memory cells. A strap connects one of the buried bitlines to a gate that underlies one of the plurality of contacts, and wherein contacts overlying a first bit line are staggered with respect to contacts overlying a second bit line that is adjacent to the first bit line.

Abstract: The present invention is directed to a method of forming halo implant regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, the substrate being doped with a first type of dopant material, and forming halo implant regions in the substrate adjacent the gate electrode by performing at least the following steps: performing a first angled implant process using a dopant material that is of a type opposite to the first type of dopant material and performing a second angled implant using a dopant material that is of the same type as the first type of dopant material. The method concludes with performing at least one additional implantation process to further form source/drain regions for the device.