Abstract: The present invention relates to a method for fabricating a semiconductor device, and to a semiconductor device, the method including providing a semiconductor substrate; depositing on the semiconductor substrate a composite dielectric material layer including elements of at least two dielectric materials, in which the step of depositing includes providing a first precursor for a first dielectric material at a first rate and providing a second precursor for a second dielectric material at a second rate, in which at least a portion of the at least two dielectric materials are deposited simultaneously. The semiconductor device includes a composite dielectric material layer having a thickness, and including elements of a first dielectric material and a second dielectric material, in which the composite dielectric material layer includes a varying concentration ratio of the first dielectric material to the second dielectric material through the thickness.

Abstract: A technique for processing a wafer in a semiconductor manufacturing process are disclosed. The method comprises first collecting a set of processing rate data from a multi-station processing tool, the set including process rate data from at least two stations in the processing tool. The collected processing rate data is then communicated to a controller that autonomously compares the processing rate data to determine whether to adjust a process parameter. The method then adjusts the process parameter for at least one station to match the process endpoint for the at least one station.

Abstract: A thin barrier layer of undoped silicon is formed on an ARC to prevent resist poisoning and footing. The silicon layer can be removed with improved yield and high selectivity with respect to the underlying gate dielectric layer, thereby avoiding degradation of the gate dielectric layer. Embodiments include forming a silicon oxynitride ARC on a polycrystalline silicon layer overlying a silicon oxide layer, depositing a thin undoped polycrystalline or amorphous silicon barrier layer on the ARC, forming a photoresist mask on the barrier layer, etching to form a gate electrode on a gate oxide layer and removing the photoresist mask. The undoped polycrystalline or amorphous silicon barrier layer is then removed employing conventional wet or dry etching techniques with high etch selectivity to the underlying gate oxide layer, thereby avoiding degradation of the gate oxide layer.

Abstract: A clock switching technique allows selecting an input clock signal from any number of clock sources. Multiplexed input clock signals are switched on the fly onto an internal clock line coupled to an output clock line. Clock glitches are allowed on the output clock line. A clock invalid signal is asserted synchronous with the internal clock line during the time clock glitches may potentially be generated. The clock invalid signal signifies that clock switching is in progress and can be used to reset circuits which use the output clock line preventing problems in those circuits typically caused by clock glitches during the period of output clock instability. The clock switching technique is independent of clock source frequency as well as the system clock frequency.

Abstract: There is provided a tester interface circuit for use with a BIST state machine and a method for micro-architectural implementation of the same so as to enable cycling through a BIST test. The tester interface circuit includes a storage device, a logic decoder, a set/clear mechanism, and a polling logic device. The tester interface circuit is implemented with a minimum amount of chip area on a semiconductor IC.

Abstract: A MOSFET and methods of fabrication. The MOSFET includes a gate having a center gate electrode portion being spaced from the layer of semiconductor material by a center gate dielectric. The gate also includes a lateral gate electrode portion adjacent each sidewall of the center gate electrode portion. The lateral gate electrode portions are each spaced from the layer of semiconductor material by a lateral gate dielectric portion.

Abstract: An arrangement for implementing a network in an ISDN-BASED customer premises having a 4-wire ISDN S0 bus. The ISDN-BASED customer premises includes a Network Termination Basic Access (NTBA) that interfaces between the residential customer premises and the public switched telephone network by mapping the 2-wire ISDN signal onto the 4-wire bus. A low pass filter is added to the 2-wire send path to eliminate high frequency noise caused by harmonic reflections of the ISDN-based signals on the 4-wire bus. The filter also provides a delay between the zero crossing of the ISDN-based signals and the transmitted network signals, minimizing the effect of the ISDN zero crossings on the home network signal.

Abstract: An apparatus is disclosed for capturing and transferring internal system activity of a computer under test. In one embodiment, the apparatus includes a bus interface, a memory, an external interface, and circuitry coupling the three together. The bus interface connects to an internal system bus of the system under test. The memory is for storing information indicative of internal system activity. The external interface couples to an external, monitoring system. The circuitry partitions the memory into at least two banks, each having multiple buffers. One of the multiple buffers in each bank is a trace buffer that receives instruction trace information from the processor of the system under test. The multiple buffers may further include a system memory image buffer, a processor data buffer, and a bus activity buffer. When any one of the buffers in a given bank of the memory becomes full, a bank switch occurs.

Abstract: A novel method of data forwarding is provided in a network switch having multiple ports including at least one backbone port for data communications with backbone network nodes. Destination information of a received data packet is compared with a predetermined set of address data in an address table. If the packet's destination information is not found in the address table, the received data packet is forwarded to the backbone port. Further, the source address information of the received data packet may be compared with the address table. In a regular mode of operation, if the packet's source address information is not found in the address table, this information is added to the address table. However, in a backbone mode of operation, the address information of a data packet received from the backbone port is prevented from being added to the address table. The switch may have backbone ports provided for multiple VLANs supported by the switch.

Abstract: A system and method for initializing deterministic source-synchronous transfers between devices in a computer system using one or more ratio bits to indicate a ratio between clocks. In an exemplary computer system, one or more processors are each coupled to a bridge. The one or more ratio bits are used to indicate a ratio between the system clock of a first device, such as a processor, and the system clock of a second device, such as the bridge. Each device may also operate at a multiple of its system clock. Once the one or more ratio bits have been stored, the first device can determine when edges of its operating clock correspond to edges of the operating clock of the second device. The use of the one or more ratio bits may advantageously allow devices in the computer system to operate on different system clocks without dedicated signal lines or pins to indicate the frequencies of those different system clocks.

Abstract: The present invention is generally directed to a method of controlling photolithography processes based upon scatterometric measurements of sub-nominal grating structures, and a system for accomplishing same. In one embodiment, the method comprises providing a library of optical characteristic traces, each of which corresponds to a sub-nominal grating structure comprised of a plurality of photoresist features having a known degree of residual photoresist material positioned between the photoresist features, forming a process layer above a semiconducting substrate, and forming a layer of photoresist above the process layer.

Abstract: A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.

Abstract: A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.

Abstract: A circuit for correction of errors in a memory device comprises a data word byte counter 16, data encoders 18 and 20, a syndrome accumulator 22, a data word byte address generator 24, a comparator 26, a decoder 28 and an error correction enable buffer 30. The error correction circuit 4 is coupled to a memory array 2 through a pre-read input-output bus 14, and is further coupled to an input-output multiplexer buffer 6 which is coupled between the memory array 2 and a data bus 12.

Abstract: In one illustrative embodiment, the method comprises performing at least one electrical performance test on an integrated circuit device, determining, based upon data obtained from said at least one electrical performance test, a target thickness for at least one inter-level dielectric layer to be formed above a wafer, and performing a deposition process to form said at least one inter-level dielectric layer to said target thickness. In other embodiments, the method comprises determining a duration of a deposition process to be performed to form the at least one inter-level dielectric layer, and performing the deposition process for the determined duration.

Abstract: An non-volatile read only memory transistor for use in a memory array is disclosed. The non-volatile read only memory transistor features a substantially vertically oriented channel fabricated in a trench formed in the substrate. The channel length is dependent upon the depth of the trench and therefore a dense array of NROM transistors can be formed without adversely affecting the channel length and therefore the operational performance of the transistor.

Abstract: MOS transistor and CMOS devices comprising a plurality of transistors including in-laid, metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal filling openings in an insulative layer at the bottom of which openings gate insulator layer segments of MOS transistor precursor regions formed in a semiconductor substrate are exposed; selectively forming at least one masking layer segment on the first blanket layer overlying selected ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or silicon over the thus-formed structure, and effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying other ones of the MOS transistor precursor regions. Unnecessary layers remaining after alloying or silicidation reaction are then removed by performing planarization processing, e.g., by CMP.

Abstract: Deleterious poisoning of patterned photoresist masking layers accompanying plasma ashing/etching of photoresist and/or low-k dielectric layers in a nitrogen-containing atmosphere is eliminated, or at least substantially reduced, by post-treating exposed surfaces of the low-k dielectric layer(s) with hydrogen, e.g. by contact with H2 gas at an elevated temperature or with a H2 plasma subsequent to plasma ashing/etching. The invention enjoys particular utility in the formation of dual damascene openings in dielectric layers as part of metallization processing of semiconductor IC devices.

Abstract: A method of fabricating a microdevice having the steps of forming a first regular array of lines and spaces from a first layer of material deposited on a substrate; patterning the first regular array of lines and spaces to form a first portion of a microdevice component; providing an intermediate layer over the first portion of the microdevice component; forming a second regular array of lines and spaces from a second layer of material deposited on the intermediate layer; patterning the second regular array of lines and spaces to form a second portion of the microdevice component; and forming contact holes in the intermediate layer to establish conductivity between the first portion of the microdevice component and the second portion of the microdevice component.

Abstract: A system adapted to provide in-situ detection of closed area defects and a method for the same is provided. The system comprises a light source for directing light on to a wafer having a grating pattern etched thereon; a light detector for collecting the light reflected from the wafer; a processor operatively coupled to the light detector for converting the collected light into data associated with the grating pattern and determining the presence of the closed area defect; and a controller operatively coupled to the processor for determining whether the wafer requires additional processing to repair the closed area defect.