Abstract: A system for regulating ON and/or ONO dielectric formation is provided. The system includes one or more light sources, each light source directing light to one or more oxide and/or nitride layers being deposited and/or formed on a wafer. Light reflected from the oxide and/or nitride layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The system also includes a plurality of oxide/nitride formers; each oxide/nitride former corresponding to a respective portion of the wafer and providing for ON and/or ONO formation thereon.

Abstract: An exemplary method of selectively patterning a hard mask or reticle using a laser to cause deposition of hard mask material in locations forming the hard mask pattern. This method can include providing a vapor in a vapor chamber containing an integrated circuit substrate, and applying a laser to selected areas of the integrated circuit substrate to cause a reaction with the vapor and create a structure on the integrated circuit substrate.

Abstract: A non-planar target can be configured for use in a plasma vapor deposition (PVD) process in which ions bombard the non-planar target and cause alloy atoms present in the non-planar target to be knocked loose and form an alloy film layer. The target includes a top planar section having a first alloy concentration and a side annular section having a second alloy concentration. The side annular section has ends coupled to ends of the top planar section. The first alloy concentration and the second alloy concentration are different.

Abstract: A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.

Abstract: A method for enhancing the operating characteristics of memory devices (400C), such as flash memory devices, by manipulating the Fermi energy levels of the substrate (406) and the floating gate (404). In so doing, the gap between the minimum conduction band energy level (408) and the Fermi energy level (412) of the floating gate (404) is extended so as to readily facilitate the movement of electrons from the substrate (406) into the floating gate (404).

Abstract: A metal gate structure and method of making the same provides a tracer layer over a first metal or metal compound layer. When etching a metal gate, formed of tungsten, for example, with a first etchant chemistry optimized for etching tungsten, detection of the tracer layer through optical emission spectroscopy, for example, indicates the imminent clearing of the tungsten. A second etchant chemistry is then employed that is selective to the first metal or metal compound layer, such as TiN, overlying the gate dielectric. This provides a controlled etching of the TiN and thereby prevents degradation of the underlying gate dielectric material.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first conductor core is connected to the semiconductor device. A low dielectric constant dielectric layer is formed over the semiconductor substrate and has an opening formed therein. A first barrier layer is deposited over the first conductor core. A second barrier layer is deposited to line the low dielectric constant dielectric layer and the first barrier layer. A third barrier layer is deposited to line the second barrier layer. A second conductor core is deposited to fill the opening over the third barrier layer.

Abstract: A system and method for calibrating/characterizing an electron beam (e-beam) defect inspection tool for detecting voltage contrast defects includes deliberately forming defects in a test portion of a semiconductor wafer by deliberately forming an open, short, or abnormal resistance in a circuit feature. The test portion can be in the scribe lines of a product die or on a fully populated test wafer, so that the calibration of the e-beam tool for certain inspection layers of a fabrication technology can be determined. The electron microscope output of the is checked against the known defects to determine whether the tool is accurately sensing defects.

Abstract: An improved flash memory device having core stacks and periphery stacks which are protected by first and second thin side walls, side spacers over the side walls, and an HTO layer over the stacks, and side spacer. The flash memory device has an intermetallic dielectric layer placed over the HTO layer. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The additional first and second side walls reduce current leakage between core stacks and the tungsten plug and help to protect the stacks during fabrication.

Abstract: A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the PVD amorphous silicon layer. Additional dopants are implanted into the PVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer, while the additional doping of the PVD amorphous silicon layer lowers the resistivity of the gate electrode.

Abstract: In one illustrative embodiment, the method includes providing a wafer including at least one non-production area, forming a process layer above the wafer, forming a masking layer above the process layer, the masking layer being patterned so as to expose a portion of the process layer formed above the at least one non-production area, and performing a process operation on the exposed portion of the process layer formed above the at least one non-production area. In another aspect, the present invention is directed to a system that includes a controller for identifying at least one non-production area of a wafer, a photolithography tool for forming a masking layer above the process layer, the masking layer being patterned so as to expose a portion of the process layer formed above the at least one non-production area, and an etch tool for performing an etching process on the exposed portion of the process layer formed above the at least one non-production area.

Abstract: An apparatus for and a method of introducing a gas into a vacuum processing chamber are provided. In one aspect, a processing apparatus is provided that includes a vacuum processing chamber, a first source of gas coupled to the vacuum processing chamber, and a fluid actuated valve for regulating the flow of the gas from the first source of gas to the vacuum processing chamber. The fluid actuated valve is operable to open in response to a flow of an actuating fluid and has a minimum valve opening pressure. A valve is provided for enabling the actuating fluid to flow to the fluid actuated valve. A controller is provided for selectively modulating the flow of the actuating fluid to the fluid actuated valve whereby the pressure of the actuating fluid is increased incrementally from an initial pressure to at least the minimum valve opening pressure. The apparatus reduces the risk of troublesome gas bursts in vacuum processing chambers.

Abstract: An integrated circuit fabrication process to pattern features having reduced pitch is disclosed herein. The process includes reducing the width of a developed exposed area of a patterned photoresist layer provided over a substrate before patterning the substrate. The process further includes additionally patterning the patterned photoresist layer using the previously used mask or reticle to form a first feature and a second feature. The distance between adjacent first and second features is smaller than the distance between either of adjacent first features or adjacent second features.

Abstract: An electrostatic discharge (ESD) protection device for a silicon-on-insulator (SOI) integrated circuit having a silicon substrate with a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer having active regions defined by isolation trenches. The ESD protection device is formed on the SOI integrated circuit and has an anode and a cathode formed within one of the active regions and coupled respectively to a first and a second node; and a backside contact plug adjacent and in thermal contact with at least one of the anode or the cathode, the backside contact plug traversing the buried oxide layer to thermally couple the one of the active regions and the substrate.

Abstract: A process for preventing deformation of patterned photoresist features during integrated circuit fabrication is disclosed herein. The process includes stabilizing the patterned photoresist features by a flood electron beam before one or more etch processes. The stabilized patterned photoresist features resist pattern bending, breaking, collapsing, or deforming during a given etch process. The electron beam stabilization can be applied to the patterned photoresist features a plurality of times as desired.

Abstract: There is provided a method of making a dual inlaid via in a first layer. The first layer may be a polymer intermetal dielectric, such as HSQ, of a semiconductor device. The method includes forming a first opening, such as a via, in the first layer and forming a bilayer resist in the first opening. The bilayer resist includes an imaging layer above a bottom antireflective coating (BARC). The imaging layer is selectively exposed to radiation such that no radiation reaches the lower section of the BARC in the first opening through the upper section of the BARC. The bilayer resist is pattered, and a second opening, such as a trench, is formed in communication with the first opening using the patterned bilayer resist as a mask.

Abstract: A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; implanting nitrogen into the sidewall spacers; forming a nickel layer; and forming nickel suicide layers disposed on the source/drain regions and the gate electrode. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600° C. The nitrogen implantation process is a plasma treating in a plasma-enhanced chemical vapor deposition chamber, and the nickel deposition is performed in a physical deposition chamber. Also, the implantation process and the formation of the nickel layer are sequentially performed without removal from a non-oxidizing atmosphere.

Abstract: A technique for processing a wafer in a semiconductor manufacturing process are disclosed. The method comprises first collecting a set of processing rate data from a multi-station processing tool, the set including process rate data from at least two stations in the processing tool. The collected processing rate data is then communicated to a controller that autonomously compares the processing rate data to determine whether to adjust a process parameter. The method then adjusts the process parameter for at least one station to match the process endpoint for the at least one station.

Abstract: A clock switching technique allows selecting an input clock signal from any number of clock sources. Multiplexed input clock signals are switched on the fly onto an internal clock line coupled to an output clock line. Clock glitches are allowed on the output clock line. A clock invalid signal is asserted synchronous with the internal clock line during the time clock glitches may potentially be generated. The clock invalid signal signifies that clock switching is in progress and can be used to reset circuits which use the output clock line preventing problems in those circuits typically caused by clock glitches during the period of output clock instability. The clock switching technique is independent of clock source frequency as well as the system clock frequency.

Abstract: A method is provided, the method comprising forming a buffer layer above a structure layer, and forming a dielectric layer above the buffer layer. The method also comprises patterning the dielectric layer to form a salicide block above a portion of the structure layer protecting the portion from a subsequent salicidation. A device is also provided, the device comprising a buffer layer above a structure layer and a dielectric layer above the buffer layer. The dielectric layer is patterned to form a salicide block above a portion of the structure layer to protect the portion from a subsequent salicidation.