Abstract: A technique for negotiating the width of a link between a first device and a second device includes detecting, during initialization, a respective signal on one or more control lines associated with at least a portion of an N-bit link. The N-bit link is configured as a single link having a width of N or multiple sublinks having a width less than N based on a respective value of the respective signal on the one or more control lines.

Abstract: A method includes determining production targets for devices of different types in a production line. A queue level of devices of a first type that have completed performance of a first operation configured in accordance with a first setup state in the production line and await performance of a second operation in the production line is determined. Based on the determined queue level, a second type of device is selected for subsequent processing in the first operation based on the production targets and a setup time associated with configuring the first operation from the first setup state to a second setup state associated with the second type of device. The first operation is configured in accordance with the second setup state for processing devices of the second type.

Abstract: A method includes determining at least a first characteristic of a device during a first test insertion and storing the first characteristic. The device is identified during a second test insertion. The first characteristic is retrieved responsive to the identification of the device. A test program for the second insertion is configured based on the first characteristic. The configured test program is executed to test the device during the second test insertion.

Abstract: A data transfer device transfers data between two clock domains of a data processing device when the data processing device is in a test mode. The data transfer device receives clock signals associated with each clock domain. To transfer data from a first clock domain to a second clock domain the data transfer device identifies transitions of clock signals associated with each clock domain that are sufficiently remote from each other so that data can deterministically be provided by one clock domain and sampled by the other. This ensures that data can be transferred between the clock domains deterministically even when the phase relationship between the clock signals is indeterminate.

Abstract: A system and method are disclosed for managing the connectivity of a mobile device to a plurality of network connectivity locations. A mobile device comprising a network connectivity manager accesses a repository of predetermined network connectivity management information stored on a network host. The network connectivity manager uses a first predetermined subset of the information to discover the presence of a first network and then manages connectivity between the mobile device and the first discovered network. A second predetermined subset of information is then used to discover the presence of a second network. The network connectivity manager then transfers the mobile device's connectivity from the first network to the second network. Transfer of connectivity is dependent upon successful submission and acceptance of predetermined user credentials and each network's compliance with predetermined connectivity policies.

Abstract: A 1.5-bit algorithmic analog-to-digital converter (ADC) generates a digital value representative of an input voltage. The ADC implements a series of conversion cycles for a conversion operation. Each conversion cycle has three sub-cycles: a scaling sub-cycle, a first sample sub-cycle, and a second sample sub-cycle. In the scaling sub-cycle, the residual voltage from the previous conversion cycle is doubled to generate a first voltage. In the first sample sub-cycle, a first bit of a corresponding bit pair is determined based on the polarity of the first voltage. The first voltage is either increased or decreased by a reference voltage based on the polarity of the first voltage to generate a second voltage. In the second sample sub-cycle, a second bit of the corresponding bit pair is determined based on the polarity of the second voltage.

Abstract: A system and method for automatically simulating the affect of a plurality of factors on the cost of goods sold (COGS) resulting from changes in the allocation of goods to be sold in a plurality of predetermined markets. A predetermined plurality of markets are defined, each of which is allocated a default percentage of total goods to be sold. A plurality of production sites are then defined, their associated cost factors determined, their respective output assigned to predetermined markets, and the weighted, average unit COGS for each market is then calculated. A defined market is then selected for sensitivity simulation and its associated sales allocation is iteratively decremented by a predetermined percentage for reallocation to other markets. Each market's weighted, average unit cost is recalculated after each iteration, and once reallocation is completed, the global, average unit COGS is calculated.

Abstract: A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure to create a well region in the semiconductor layer that is directly coupled to the trench capacitor. A gate structure is formed overlying a portion of the well region. Conductivity determining ions are then implanted into other portions of the well region to form a source region and a drain region, and to define an active body region between the source region and the drain region. The active body region directly contacts the trench capacitor.

Abstract: A circuit including is disclosed. The circuit includes a precharge circuit configured to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase, and an evaluation circuit configured to, during an evaluation phase, pull the dynamic node toward a ground voltage responsive to a first input condition and configured to inhibit pulling of the dynamic node down responsive to a second input condition. A pull-up circuit coupled between the first dynamic node and the voltage supply node includes first and second pull-up transistors. The first pull-up transistor is configured to activate responsive to the precharge phase. The second pull-up transistor is configured to activate at a delay time subsequent to entry of the evaluation phase. When the first and second pull-up transistors are active, a pull-up path is provided between the dynamic node and the voltage supply node.

Abstract: By providing an under-specified specification for designating a destination carrier in a respective control job or control message, a high degree of flexibility in determining the destination of processed substrates may be obtained, thereby also allowing the removal of a source carrier for enhancing load port availability in complex semiconductor facilities.

Abstract: By performing a two-step approach for predicting a quality distribution during the fabrication of semiconductor devices, enhanced flexibility and efficiency may be accomplished. The two-step approach first models electrical characteristics on the basis of measurement data, such as inline measurement data, and, in a second step, an appropriate distribution for the electrical characteristics may be established, thereby obtaining modeled wafer sort data which may then be used for predicting a quality distribution of the semiconductor devices under consideration.

Abstract: A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF4) and trifluoromethane (CHF3) to etch at least the control gate layer.

Abstract: Various stacked semiconductor devices and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor die that has a first bulk semiconductor side and a first opposite side. A second semiconductor die is provided that has a second bulk semiconductor side and a second opposite side. The second opposite side of the second semiconductor die is coupled to the first opposite side of the first semiconductor die. Electrical connections are formed between the first semiconductor die and the second semiconductor die.

Abstract: A system and method of allocating registers in a register array to multiple workloads is disclosed. The method identifies an incoming workload as belonging to a first process group or a second process group, and allocates one or more target registers from the register array to the incoming workload. The register array is logically divided to a first ring and a second ring such that the first ring and the second ring have at least one register in common. The first process group is allocated registers in the first ring and the second process group is allocated registers in the second ring. Target registers in the first ring are allocated in order of sequentially decreasing register addresses and target registers in the second ring are allocated in order of sequentially increasing register addresses.

Abstract: A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage.

Abstract: A circuit includes a memory circuit. The memory retiling circuit moves image information configured to be distributed among a plurality of memory channels into reconfigured image information configured to be distributed among a subset of the plurality of memory channels.

Abstract: A method, apparatus, and a system for prioritizing processing of a workpiece is provided. At least one workpiece is processed. A tag associated with the workpiece is provided. The tag includes process priority data for determining an order relating to processing the workpiece.

Abstract: A system, method and program code are disclosed for the unattended monitoring, retrieval and storage of online content by a mobile information processing system operating in a low power mode. An intelligent wireless modem is activated when a mobile information processing system is operating in a low power state. The intelligent wireless modem detects the availability of a predetermined wireless network and establishes a connection. Predetermined online sites and services are then monitored by an unattended online content processor for the identification, retrieval, and subsequent storage of predetermined content. The stored content is subsequently retrieved and presented to the user for review and other operations when the mobile information processing system enters an initialization state.

Abstract: A video processing apparatus and methodology use a combination of a processor and a video decoding hardware block to decode video data by using a reference block cache memory to perform motion compensation decode operations in the video decoding hardware block. To improve the cache hit rate, each memory access for required reference block(s) is used to fetch one or more additional reference blocks which can be used to improve the cache hit rate with future motion compensation operations. Speculative fetch control logic selects the additional reference blocks by using a frequency history table to accumulate compared motion vector information for a current motion compensation block with motion vector information from previously processed motion compensation blocks.