Abstract: According to one exemplary embodiment, a method for modifying a shared data queue accessible by a plurality of processors comprises receiving an instruction from one of the processors to produce a modification to the shared data queue, running a microcode program in response to the instruction, to attempt to produce the modification, and generating a final datum to signify whether the modification to the shared data queue has occurred. In one embodiment, the modification comprises enqueuing data, and running the microcode program includes checking writability of a write pointer of the shared data queue, checking writability of a data field designated by the write pointer, locking the write pointer and checking the old value of its lock bit with atomicity, writing the data to the data field and incrementing the write pointer by the size of the data, and unlocking the write pointer.

Abstract: Methods and apparatus for aligning a clock signal and a set of strobe signals are disclosed. In one embodiment, a memory controller includes a clock generator configured to generate the clock signal, and a respective strobe signal generator configured to generate each strobe signal. The memory controller further includes a phase recovery engine configured to receive an error signal from a corresponding memory device, wherein the error signal conveys an error indication indicative of an alignment of the strobe signal relative to the clock signal for each of a plurality of cycles of the strobe signal. The phase recovery engine includes an accumulator configured to maintain an accumulation value that depends upon the error indications for the plurality of cycles of the strobe signal. The strobe signal generator is configured to control a delay associated with generation of the strobe signal depending upon the accumulation value.

Abstract: Unitary transceiving units employ a multiple carrier, time-division-multiple-access (TDMA), time-division-duplex (TDD protocol to conduct concurrent wireless voice and data communications wherein a first transceiving base station unit tethered to a network interface wirelessly communicates to a second, mobile transceiving unit. The mobile transceiving unit wirelessly transmits and receives packetized voice and data information that is separated and routed to respective voice or data networks. The unitary mobile transceiving unit thus functions as a concurrent voice phone and data communications terminal/computer.

Abstract: A division method includes determining a precision indicator for the division operation that indicates whether the quotient should be a single precision, double precision, or extended precision floating-point number. The division is performed at a rectangular multiplier using the Goldschmidt or Newton-Raphson algorithm. Each algorithm calculates one or more intermediate values in order to determine the quotient. For example, the Goldschmidt algorithm calculates a complement of a product of the dividend and an estimate of the reciprocal of the divisor. The quotient is determined based on a portion of one or more of these intermediate values. Because only a portion of the intermediate value is used, the division can be performed efficiently at the rectangular multiplier, and therefore the quotient can be determined more quickly and still achieve the desired level of precision.

Abstract: A device includes a memory configured so that, in the event that one pass-gate transistor associated with a bit cell is determined to be excessively weak such that reading the bit cell could be undesirably difficult, a second pass-gate transistor can be configured to support a read operation. For example, during a manufacturing test procedure, the access speed of each bit cell at a memory device is determined. If a bit cell fails to achieve a desired access speed, the column of the memory that includes the defective bit cell can be configured to access information stored at the bit cell using the second bit line associated with the second pass-gate transistor.

Abstract: The present invention facilitates overall system performance by balancing system resource utilization and network throughput. The invention analyzes packets received from host software selects one or more of buffers to coalesce into a single, coalesced buffer. The selection is based upon an initial fragment size selected to facilitate overall system performance. The coalesced buffer and non-coalesced buffers, are passed to a network device for transmission.

Abstract: By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.

Abstract: One set of illegal vector sequences is manually generated for a circuit design and a symbolic simulator is used to automatically generate another set of illegal vector sequences for the circuit design. For verification purposes, the relationship between the manually generated set and the automatically generated set is determined. Prior to determining this relationship, one or both of the sets are simplified. One simplification technique includes replacing pairs of illegal vector sequences that are the same except at one bit position with a more general illegal vector sequence representative of both illegal vector sequences of the pair.

Abstract: Techniques for performing DC to DC power conversion in switch-mode converter circuits include combinations of dynamic switch shedding, phase shedding, symmetric phase circuit topologies, and asymmetric phase circuit topologies. In at least one embodiment of the invention, a method of operating a power converter circuit includes operating a first phase switch circuit portion using a first number of switch devices when the power converter circuit is configured in a first mode of operation. The first number is greater than zero. The method includes operating the first phase switch circuit portion using the first number of switch devices when the power converter circuit is configured in a second mode of operation. The method includes operating a second phase switch circuit portion using a second number of switch devices when the power converter circuit is configured in the second mode of operation. The second number is greater than the first number.

Abstract: A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.

Abstract: By incorporating a material exhibiting a high adhesion on chamber walls of a process chamber during sputter etching, the defect rate in a patterning sequence on the basis of an ARC layer may be significantly reduced, since the adhesion material may be reliably exposed during a sputter preclean process. The corresponding adhesion layer may be positioned within the ARC layer stack so as to be reliably consumed, at least partially, while nevertheless providing the required optical characteristics. Hence, a low defect rate in combination with a high process efficiency may be achieved.

Abstract: A processor can operate in three different modes. In an active mode, a first voltage is provided to the processor, where the first voltage is sufficient to allow the processor to execute instructions. In a low-power mode, a retention voltage is provided to the processor. The processor consumes less power in the retention mode than in the active mode. In addition, the processor can operate in a third mode, where a voltage is provided to the processor sufficient to allow the processor to process cache messages, such as coherency messages, but not execute other normal operations or perform normal operations at a very low speed relative to their performance in the active mode.

Abstract: In one embodiment, an apparatus comprises one or more processors and a controller coupled to the processors. Each processor comprises at least one processor time stamp counter (TSC) and a first control unit configured to maintain the processor TSC. The controller comprises at least one controller TSC and a second control unit configured to maintain the controller TSC. The controller is configured to signal the processor responsive to determining that the processor TSC is out of synchronization with the controller TSC. In response to having been signalled that the processor TSC is out of synchronization, the processor is configured to resynchronize the processor TSC to the controller TSC before generating a result for a read TSC instruction. In response to having not been signalled that the processor TSC is out of synchronization, the processor is configured to generate the result responsive to the processor TSC without resynchronizing.

Abstract: A memory device is disclosed that includes a plurality of word-lines, with each word-line connected to at least one bitcell. Each of the plurality of word-lines is connected to a corresponding driver module to drive the word-line in response to a corresponding select signal. Further, each driver module is connected to a level shifter to shift the corresponding select signal so that the driver module provides a level-shifted signal at the first word-line in response to assertion of the first select signal. A single level shifter can be connected to multiple driver modules, thereby reducing the area required to implement level-shifting for multiple word-lines.

Abstract: A memory device is provided which includes a write bit line, a read bit line, and at least one memory cell. The memory cell includes a write access transistor, a read access transistor coupled to the read bit line and to the first write access transistor, and a gated-lateral thyristor (GLT) device coupled to the first write access transistor. Among its many features, the memory cell prevents read disturbances during read operations by decoupling the read and write bit lines.

Abstract: By forming a first portion of a substrate contact in an SOI device on the basis of a trench capacitor process, the overall manufacturing process for patterning contact elements may be enhanced since the contacts may only have to extend down to the level of the semiconductor layer. Since the lower portion of the substrate contact may be formed concurrently with the fabrication of trench capacitors, complex patterning steps may be avoided which may otherwise have to be introduced when the substrate contacts are to be formed separately from contact elements connecting to the device level.

Abstract: An apparatus includes a first module and a second module. The first module provides a challenge. The second module performs a signature function in response to the challenge. The first module authenticates the second module based on a time required by the second module to complete the signature function and/or an amount of power consumed by the second module to complete the signature function.

Abstract: In one embodiment, a processor comprises a plurality of registers configured to store processor state and an execution core coupled to the registers. The execution core is configured, during a switch between processor execution of a guest and processor execution of a virtual machine manager (VMM) that controls the guest, to save only a portion of the processor state to a memory. In another embodiment, a method comprises switching from processor execution of a first one of a guest and a virtual machine manager (VMM) to processor execution of a second one of the guest and the VMM, wherein the VMM controls execution of the guest; and during the switching, the processor saving only a portion of a processor state to memory.

Abstract: A system and method for providing a digital real-time voltage droop detection and subsequent voltage droop reduction. A scheduler within a reservation station may store a weight value for each instruction corresponding to node capacitance switching activity for the instruction derived from pre-silicon power modeling analysis. For instructions picked with available source data, the corresponding weight values are summed together to produce a local current consumption value and this value is summed with any existing global current consumption values from corresponding schedulers of other processor cores yielding an activity event. The activity event is stored. Hashing functions within the scheduler are used to determine both a recent and an old activity average using the calculated activity event and stored older activity events.

Abstract: In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coupled to the microcode memory, the sequence control unit is configured to control reading microcode operations from the microcode memory to be issued for execution by the processor. The sequence control unit is configured to stall issuance of microcode operations forming a body of a loop in a first routine of the plurality of microcode routines until a loop counter value that indicates a number of iterations of the loop is received by the sequence control unit.