Abstract: A method and apparatus for restricting the execution of security sensitive instructions. A first security identification (ID) is associated with each of a plurality of instructions or a set of instructions that are to be executed by a processor. Software code running on the processor requests to execute at least one of the plurality of instructions or set of instructions. The processor obtains a second security ID associated with the software code running thereon and compares the second security ID with the first security ID. The processor executes the requested instruction or set of instructions providing that the second security ID matches the first security ID.

Abstract: By introducing a atomic species, such as carbon, fluorine and the like, into the drain and source regions, as well as in the body region, the junction leakage of SOI transistors may be significantly increased, thereby providing an enhanced leakage path for accumulated minority charge carriers. Consequently, fluctuations of the body potential may be significantly reduced, thereby improving the overall performance of advanced SOI devices. In particular embodiments, the mechanism may be selectively applied to threshold voltage sensitive device areas, such as static RAM areas.

Abstract: Systems and methods for improved vector data processing based on separately processing elements of a vector in multiple simultaneously executing vector element processing units are disclosed. One embodiment of the present invention is a vector processing system including a plurality of vector element processing units and a routing infrastructure. The routing infrastructure is configured to route each element of a received vector to a respective one of the vector element processing units. The received vector may be from a memory which is coupled to the vector element processing units by the routing infrastructure. Each vector element processing unit is configured to simultaneously process two or more elements, wherein each of the two or more elements is from a separate vector. Embodiments of the present invention also provide for forwarding of data and results of computation between vector element processing units.

Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.

Abstract: In one disclosed embodiment, the present method for determining resist suitability for semiconductor wafer fabrication comprises forming a layer of resist over a semiconductor wafer, exposing the layer of resist to patterned radiation, and determining resist suitability by using a scatterometry process prior to developing a lithographic pattern on the layer of resist. In one embodiment, the semiconductor wafer is heated in a post exposure bake process after scatterometry is performed. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source in a lithographic process. In other embodiments, patterned radiation is provided by an electron beam, or ion beam, for example. In one embodiment, the present method determines out-gassing of a layer of resist during exposure to patterned radiation.

Abstract: Apparatus and methods for assembling semiconductor chips packages are provided. In one aspect, a method of manufacturing is provided that includes placing a first set of semiconductor chip package substrates in a first group of receptacles of a first processing station. Each of the first set of semiconductor chip package substrates has a first footprint. The receptacles of the first group being dimensioned to accommodate the first footprint. A second set of semiconductor chip package substrates is placed in a second group of receptacles of the first processing station. Each of the second set of semiconductor chip package substrates has a second footprint larger than the first footprint. The receptacles of the second group being dimensioned to accommodate the second footprint. A first set of lids is placed on the first set of semiconductor chip package substrates and a second group of lids is placed on the second set of semiconductor chip package substrates.

Abstract: A graphene-based device is formed with a trench in one or more layers of material, a graphene layer within the trench, and a device structure on the graphene layer and within the trench. Fabrication techniques includes forming a trench defined by one or more layers of material, forming a graphene layer within the trench, and forming a device structure on the graphene layer and within the trench.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising at least one transistor element. An etch stop layer is formed over the transistor element. A stressed first dielectric layer is formed over the etch stop layer. A protective layer adapted to reduce an intrusion of moisture into the first dielectric layer is formed over the first dielectric layer. At least one electrical connection to the transistor element is formed. At least a portion of the protective layer remains over the first dielectric layer after completion of the formation of the at least one electrical connection.

Abstract: By performing an anisotropic resist modification prior to the actual resist trimming process, the profile of the end portions of the resist features may be significantly enhanced, for instance by providing substantially vertical sidewall portions. Consequently, an overlap of gate electrodes with the respective isolation structures may be obtained, while nevertheless the probability for a short circuit between opposing end portions of the gate electrodes may be significantly reduced, thereby providing the potential for further scaling down device dimensions.

Abstract: A cache memory system includes a cache memory and a block replacement controller. The cache memory may include a plurality of sets, each set including a plurality of block storage locations. The block replacement controller may maintain a separate count value corresponding to each set of the cache memory. The separate count value points to an eligible block storage location within the given set to store replacement data. The block replacement controller may maintain for each of at least some of the block storage locations, an associated recent access bit indicative of whether the corresponding block storage location was recently accessed. In addition, the block replacement controller may store the replacement data within the eligible block storage location pointed to by the separate count value depending upon whether a particular recent access bit indicates that the eligible block storage location was recently accessed.

Abstract: A mechanism for suppressing instruction replay includes a processor having one or more execution units and a scheduler that issue instruction operations for execution by the one or more execution units. The scheduler may also cause instruction operations that are determined to be incorrectly executed to be replayed, or reissued. In addition, a prediction unit within the processor may predict whether a given instruction operation will replay and to provide an indication that the given instruction operation will replay. The processor also includes a decode unit that may decode instructions and in response to detecting the indication, may flag the given instruction operation. The scheduler may further inhibit issue of the flagged instruction operation until a status associated with the flagged instruction is good.

Abstract: A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.

Abstract: By providing a substantially non-damaged semiconductor region between a pre-amorphization region and the gate electrode structure, an increase of series resistance at the drain side during the re-crystallization may be reduced, thereby contributing to overall transistor performance, in particular in the linear operating mode. Thus, symmetric and asymmetric transistor architectures may be achieved with enhanced performance without unduly adding to overall process complexity.

Abstract: A method of fabricating a semiconductor device using lithography. The method can include providing a wafer assembly having a layer to be processed disposed under a photo resist layer and illuminating the wafer assembly with an exposure dose transmitted through a birefringent material disposed between a final optical element of an imaging subsystem used to transmit the exposure dose and the photo resist layer. Also disclosed is a wafer assembly from which at least one semiconductor device can be fabricated. The wafer assembly can include a layer to be processed, a photo resist layer disposed over the layer to be processed and a contrast enhancing, birefringent top anti-reflecting coating (TARC).

Abstract: An oscillator. The oscillator includes a first ring oscillator having a first plurality of inverters, a first plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the first plurality of inverters, a second ring oscillator having a second plurality of inverters, and a second plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the first plurality of capacitors is coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the second plurality of capacitors is coupled to an output terminal of a corresponding one of the first plurality of inverters. The oscillator is configured to provide as an output a differential clock signal.

Abstract: In one embodiment, an input/output memory management unit (IOMMU) comprises a control register configured to store a base address of a set of translation tables and control logic coupled to the control register. The control logic is configured to respond to an input/output (I/O) device-initiated request having an address within an address range of an address space corresponding to a peripheral interconnect. One or more operations other than a memory operation are associated with the address range, and the control logic is configured to translate the address to a second address outside of the address range if the translation tables specify a translation from the address to the second address, whereby a memory operation is performed in response to the request instead of the one or more operations associated with the address range.

Abstract: A method includes receiving fault classification data associated with a fault condition and estimating at least one yield parameter based on the fault classification data. A system includes a fault classification unit and a yield estimation unit. The fault classification unit is adapted to generate fault classification data associated with a fault condition, and the yield estimation unit is adapted to estimate at least one yield parameter based on the fault classification data.

Abstract: Various probe substrates for probing a semiconductor die and methods of use thereof are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first matrix array of conductor pins and a second matrix array of conductor pins on a probe substrate. The second matrix array of conductor pins is separated from the first matrix array of conductor pins by a first pitch along a first axis selected to substantially match a second pitch between a first semiconductor die and a second semiconductor die of a semiconductor workpiece.

Abstract: Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.

Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.