Abstract: By operating an implantation tool with a source gas having a halogen fraction of 66 atomic percent or less relative to the total composition of the source gas, an in situ cleaning effect may be achieved while performing an implantation process.

Abstract: Resist masks exposed to high-dose implantation processes may be efficiently removed on the basis of a combination of a plasma-based etch process and a wet chemical etch recipe, wherein both etch steps may include a highly selective etch chemistry in order to minimize substrate material loss and thus dopant loss in sophisticated semiconductor devices. The first plasma-based etch step may provide under-etched areas of the resist mask, which may then be efficiently removed on the basis of the wet chemical etch process.

Abstract: An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.

Abstract: According to one exemplary embodiment, a computer implemented method for detecting multiple failure modes in a set of electromigration failure data points includes sorting the data points by time to failure and dividing the data points to form first and second groups of data points to determine a first combination of first and second seed groups of data points providing an initial highest weighted R-square. The method further includes defining an intermediate group of data points shared between the first and second seed groups of data points and grouping the intermediate group of data points with the first and second seed groups of data points to determine a second combination of the first and second seed groups of data points providing a final highest weighted R-square. The initial highest weighted R-square is then compared to the final highest weighted R-square.

Abstract: A negative differential resistance (NDR) diode and a memory cell incorporating that NDR diode are provided. The NDR diode comprises a p-type germanium region in contact with an n-type germanium region and forming a germanium pn junction diode. A first gate electrode overlies the p-type germanium region, is electrically coupled to the n-type germanium region, and is configured for coupling to a first electrical potential. A second gate electrode overlies the n-type germanium region and is configured for coupling to a second electrical potential. A third electrode is electrically coupled to the p-type germanium region and may be coupled to the second gate electrode. A small SRAM cell uses two such NDR diodes with a single pass transistor.

Abstract: The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, a memory system, and a security system. The security system is coupled to the memory system and is adapted to selectively perform security processing on incoming and outgoing data. For at least one of receive or transmit processing, the security system comprises one or more encryption pipelines and at least two sets of one or more authentication pipelines. The encryption pipelines are adapted to perform one or more encryption or decryption algorithms. The authentication pipelines are adapted to perform one or more authentication algorithms. The security system is configured to selectively process frames through the encryption pipelines and then through the two sets of authentication pipelines. The system toggles whereby successive frames alternate between the two sets of authentication pipelines.

Abstract: A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.

Abstract: A method includes generating a plurality of bid requests for processing a workpiece. Each bid request is associated with one of a plurality of resources capable of processing the workpiece. For each of the bid requests, a commitment window including a kernel specifying a time period required for processing the workpiece is generated. A first committed capacity of the associated resource is determined based on a schedule of engagements compatible with the processing required for the workpiece. A second committed capacity of the associated resource is determined based on a schedule of engagements not compatible with the processing required for the workpiece. A first rate function specifying a processing cost for the associated resource as a function of the first and second committed capacities is provided. The first and second committed capacities and the first rate function are combined to generate a basic cost function associated with the associated resource.

Abstract: According to one exemplary embodiment, a test device includes a transistor situated on a substrate. The test device further includes a protection device coupled by a fuse to a gate of the transistor in an interconnect metal layer, where the interconnect metal layer is formed over the substrate. The fuse allows the protection device to be decoupled from the gate of the transistor prior to testing the transistor. The test device further includes first and second contact pads formed over the substrate and coupled to respective terminals of the fuse to provide access to the fuse. A current can be applied between the first and second contacts pads to cause the fuse to open to decouple the protection device from the gate of the transistor. The test device further includes an antenna coupled to the gate of the transistor with interconnect metal segments for accumulating electrical charge during wafer processing.

Abstract: A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal.

Abstract: A method for optimizing the performance of a media acceleration engine which includes providing input data to a replica of a media acceleration engine wherein the input data including a complete set of media streams, processing the input data via the replica of the media acceleration engine to provide replica output data, providing a subset of the complete set of media streams to a design of the media acceleration engine, simulating the operation of the design of the media acceleration engine using the subset of the complete set of media streams to provide design output data, comparing the replica output data with respective design output data, and comparing the performance of the media acceleration engine when replica output data matches corresponding design output data, is disclosed.

Abstract: Various stacked semiconductor devices and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor die that has a first bulk semiconductor side and a first opposite side. A second semiconductor die is provided that has a second bulk semiconductor side and a second opposite side. The second opposite side of the second semiconductor die is coupled to the first opposite side of the first semiconductor die. Electrical connections are formed between the first semiconductor die and the second semiconductor die.

Abstract: OPC results may be efficiently evaluated on the basis of a test structure containing a plurality of line features with opposing end portions. Thus, for different line parameters, the effect of OPC may be determined for a given critical tip-to-tip distance by determining the leakage behavior of the test assemblies, each having different design parameter values for line width and lateral distance between adjacent lines.

Abstract: A system and method for a distributed directory cache in a computing system. A system comprises a plurality of nodes including at least a source node, home node, and one or more target nodes. The source node is configured to convey a request to a home node for a coherency unit, wherein the coherency unit corresponds to a super line which comprises a plurality of coherency units including the requested coherency unit. Prior to conveying the request, the source node is configured to indicate that the request is a non-probing request responsive to determining that none of the plurality of coherency units of the super line are cached in any of the other nodes. In response to receiving the request, the home node is configured to initiate the conveyance of one or more probes to one or more target nodes, if the response does not indicate it is a non-probing request, and inhibit the conveyance of the probes if the request indicates it is a non-probing request.

Abstract: A method includes determining a transmission of a transmissive window and a transmission of a transmissive fluid. In addition, an infrared emission of the transmissive window is determined along with an infrared emission of the transmissive fluid for at least one temperature. In a system that has an infrared sensor and an optical pathway to the infrared sensor, the transmissive window and the transmissive fluid are placed in the optical pathway. A semiconductor chip is placed in the optical pathway proximate the transmissive fluid. Radiation from the optical pathway is measured with the infrared sensor. An emissivity of the semiconductor chip is determined using the measured radiation and the determined transmissions and emissions of the transmissive window and the transmissive fluid.

Abstract: Various apparatus and methods of monitoring endcap pullback are disclosed. In one aspect, an apparatus is provided that includes a substrate that has a plurality of semiconductor regions. Each of the plurality of semiconductor regions has a border with an insulating structure. A transistor is positioned in each of the plurality of semiconductor regions. Each of the transistors includes a gate that has a first lateral dimension and an end that has a position relative to its border. A voltage source is electrically coupled to the transistors whereby levels of currents flowing through the transistors are indicative of the positions of the ends of the gates relative to their borders.

Abstract: A method and an apparatus for processing semiconductor wafer based upon end-of-line (EOL) parameters. A target end-of-line parameter relating to a semiconductor wafer is determined. An inline parameter relating to processing of the semiconductor wafer is controlled in response to the target end-of-line parameter using a controller. Controlling the inline parameter includes adjusting a target inline parameter that correlates to the inline parameter.

Abstract: A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching to form a trench disposed between the first portion and the second portion of the substrate, and filling the trench with an insulating material.

Abstract: A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.

Abstract: Methods and devices are provided for protecting semiconductor devices against electrostatic discharge events. An electrostatic discharge protection device comprises a silicon substrate, a P+-type anode region disposed within the silicon substrate, and an N-well device region disposed within the silicon substrate in series with the P+-type anode region. A first P-well device region is disposed within the silicon substrate in series with the first N-well device region and an N+-type cathode region is disposed within the silicon substrate. A gate electrode is disposed at least substantially overlying the first N-well and P-well device regions of the silicon substrate.