Abstract: A first error detection for a first data word is performed using a first error correction code associated with the first data word. In response to the first error detection indicating a first uncorrectable error at the first data word based upon the first error correction code, a second error detection for a plurality of data words including the first data word and a second data word is performed using a second error correction code based upon the first and second data words.

Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Abstract: An electronic system includes a counter and a first component. The first component includes a reset input configured to receive a reset event, an interface to a communications interface coupleable to a second component, an error detection module configured to initiate the counter in response to detecting an error in a first communication from the second component, and an event logging module. The event logging module is configured to store a first indicator representative of the counter value of the counter in response to receiving the reset event via the reset input and configured to store a second indicator representative of the error at the communications interface. The counter is initiated at the first component in response to detecting an error in a first communication from the second component. A counter value of the counter is determined in response to detecting a reset event at the first component subsequent to detecting the error in the first communication.

Abstract: By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

Abstract: One aspect of the invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, a memory system, and a security system. The media access control system comprises one or more local buffers and is adapted to read a second data frame from the memory system while a first data frame is being transmitted to the network. The invention is particularly useful when the memory system has a single memory sharing several clients. When a memory has several clients, there can be instances where a read of the memory by the media access control system is delayed because the memory is busy with a request from another client. The invention helps ensure that such delays do not result in transmission errors and reduces the effect of such delays on overall transmission speed.

Abstract: In a personal Internet communication device, a system for restricting the ability of a user to transfer content from within a personal internet communicator includes non-user content stored within a system partition and user data stored within a user partition and an operating system controlling user access so that a user may not access the non-user content stored within the system partition.

Abstract: A method and apparatus detects a presence of a change in encryption status of video information, such as a preview, in a video stream. The method and apparatus issues notification information such as through a visual user interface, audibly or in any other suitable manner, that new content, such as a pay per view video information, is either available or unavailable based on the detection of a change in encryption status of the video information. An interactive and automated technique is provided to inform a user while, for example, the user is watching a display device, that a preview of content is now available or that a previously available preview has now changed and is now encrypted and therefore a user must order the previewed content before an expiration period occurs.

Abstract: An automated throughput control system and method is provided. By gathering tool specific information of a plurality of process tools on entity level, appropriate throughput related performance characteristics may be calculated with high statistical significance during moderately short time intervals. Moreover, the performance characteristics obtained from tool information may be compared to reference data, for instance provided by dynamic simulation calculations, to identify high, as well as low, performing equipment on the basis of standard process control mechanisms.

Abstract: A method and circuit for fast flag generation. The circuit is coupled to receive data to be shifted, the data including a first plurality of bits. A shift count value (including a second plurality of bits) is also received by the circuit, as well as an indication of a direction the data is to be shifted. Based on the shift count value and the indication of direction, the position of a bit within the data is determined. The bit is then output as a flag bit.

Abstract: A device includes a fin, a first gate and a second gate. The first gate is formed adjacent a first side of the fin and includes a first layer of material having a first thickness and having an upper surface that is substantially co-planar with an upper surface of the fin. The second gate is formed adjacent a second side of the fin opposite the first side and includes a second layer of material having a second thickness and having an upper surface that is substantially co-planar with the upper surface of the fin, where the first thickness and the second thickness are substantially equal to a height of the fin.

Abstract: By introducing an additional heat treatment prior to and/or after contacting a sensitive dielectric material with wet chemical agents, such as an electrolyte solution, enhanced performance with respect to leakage currents or dielectric strength may be accomplished during the fabrication of advanced semiconductor devices. For example, metal cap layers for metal lines may be provided on the basis of electroless deposition techniques, wherein the additional heat treatment(s) may provide the required electrical performance.

Abstract: System and method for decompressing data. A compressed data stream including contiguous variable length data blocks is received, each variable length data block including multiple contiguous variable length data fields. A current data block of the contiguous variable length data blocks is stored in one or more registers of a processor. Decoding state information is stored in another register of the processor. A single machine instruction of the processor is loaded. The instruction includes one or more operands corresponding respectively to the one or more registers, and another operand corresponding to the other register, where the other register is further operable as a destination register to store a result of the machine instruction. The instruction is executed to decompress the current data block using the stored decoding state information, including storing the decompressed current data block in the other register. The decompression is repeated for subsequent blocks in the stream.

Abstract: A system and method for reducing power consumption within a flip-flop circuit on a semiconductor chip. A gated input clock signal is received by a slave latch. The gated input clock is derived from an ungated input clock signal and a clock gating condition. The clock gating condition determines when an input data signal of the flip-flop and the stored internal state of the slave latch have the same logic value, such as only a logic low value. If they have the same value, toggling of the ungated input clock signal is not received by the slave latch, signal switching of internal nodes of the slave latch is reduced, and power consumption is reduced.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.

Abstract: A device and method is illustrated to prefetch information based on a location of an instruction that resulted in a cache miss during its execution. The prefetch information to be accessed is determined based on previous and current cache miss information. For example, information based on previous cache misses is stored at data records as prefetch information. This prefetch information includes location information based on an instruction that caused a previous cache miss, and is accessed to generate prefetch requests for a current cache miss. The prefetch information is updated based on current cache miss information.

Abstract: Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface.

Abstract: A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.

Abstract: Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, etching recesses into the substrate using the gate electrode as an etch mask, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

Abstract: A method and apparatus for powering up an integrated circuit (IC). An IC includes a plurality of power domains each coupled to receive power from one of a plurality of power sources. Each power domain includes a power-sensing unit. A power-sensing unit in a first one of the plurality of power domains is coupled to receive a first power ok signal from an upstream power domain, and is configured to assert a second power ok signal to be provided to a second power domain. A power-sensing unit in the second power domain is coupled to detect the presence of voltage in the first power domain, and to receive the first power ok signal. When the power-sensing unit in the second power domain has both sensed the presence of power in the first power domain and received the second power ok signal, a third power ok signal is asserted.

Abstract: Methods are provided for the fabrication of abrupt and tunable offset spacers for improved transistor short channel control. The methods include the formation of a gate electrode within a dielectric layer, with only a top portion of the gate electrode exposed. Silicon is added on the top portion of the gate electrode, by selective epitaxial growth, for example. Etching of the dielectric layer is performed with added silicon at the top portion of the gate electrode serving as a silicon mask to prevent etching of the dielectric layer directly underneath the silicon mask, which includes overhangs over the gate electrode sidewalls. The etching creates offset spacers in a production-worthy manner, and can be used to form offset spacers that are asymmetrical in width. By running the methodology in a microloading regime, wider offset spacers may be created on narrower polysilicon gate features, thereby improving Vt roll-off.